利用決策樹改善以 FPGA 為基礎之入侵偵測系統資源利用

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姓名

魏雅笛(Ya-Ti Wei) 查詢紙本館藏

畢業系所

資訊管理學系

論文名稱

利用決策樹改善以 FPGA 為基礎之入侵偵測系統資源利用
(Using Decision Trees to Improve Resource Utilization on FPGA-based Network Intrusion Detection System)

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摘要(中)

網路的應用對於目前個人及企業越來越重要，網路的頻寬也不斷的成長，網
路入侵測系統基於特徵比對便成為個人及企業不可或缺的基礎防謢。然而目前入
侵偵測系統大多架設在軟體的架構之上，越來越無法應付目前網路現況；相反地，
硬體具有高速及帄行比對能力，能夠進行快速的比對，尤其 FPGA 能重覆燒錄及
快速製作雛型，相當合適設計入侵偵測系統。但 FPGA 內所能使用的資源有限，
而特徵資料庫卻需要不斷的更新及擴張，故本研究基於以上動機，利用 FPGA 設
計入侵偵測系統，以決策樹處理規則的標頭，再依規則標頭比對架構建置多字串
比對群組來進行封包內容的比對。本研究提出的架構帄均可以降低 56%的電路資
源使用率，故能擁有更多資源來擴充新的規則，具有可擴張性，而且採用多字串
比對群組，可以使用特徵字串帄行比對增加效能，實驗証明本系統架構可以使用
較少的資源，且較其它 FPGA 設計更具效能。

摘要(英)

As network services become more and more important in our society, the demand
for network security systems is increasing. Network intrusion detection systems (NIDS)
provide an effective and secure solution to the network attacks and are widely used in
enterprises. Many NIDSs, such as Snort, are based on software, so their processing
speeds are much slower than wire-speed. FPGA technology has properties which are
high speed string matching and reprogrammable, but the resources in FPGA are limited
while the database of signatures has become very large and keeps growing.
In this thesis we use decision tree to improve the utilization of resources when
implementing NIDS on FPGA. The system uses decision tree to process the rule
header to reduce resource requirements. Rule options are organized to multiple string
matching groups according to the matching results of rule header. We implement an
IDS circuit that process 1023 Snort rules at FPGA. The experimental results show
that the system can reduce the average of resource by 56%.
In addition, we develop a tool to automatically generate the Verilog HDL source
code of the IDS circuit from a Snort rule set. Using the FPGA and the IDS circuit
generator, the proposed system is able to update the matching rule corresponding to
new intrusion and attacks.

關鍵字(中)

★ 入侵偵測系統
★ 非決定性有限狀態自動機
★ 決策樹
★ 現場可規劃邏輯閘陣列

關鍵字(英)

★ Network intrusion detection systems (NIDS)
★ Decision tree
★ NFA
★ FPGA

論文目次

中文摘要 I
英文摘要 II
圖目錄 V
表目錄 VII
第一章緒論 …………………………….. 1
1.1 研究背景 1
1.2 研究動機與目的 3
1.3 研究方法及定義 5
1.4 研究貢獻 5
1.5 章節架構 6
第二章相關研究 7
2.1 FPGA簡介 7
2.1.1 FPGA設計流程 8
2.1.2 FPGA實作開發 10
2.1.3 FPGA效能評估 10
2.2 規則標頭 14
2.2.1 基於軟體架構的標頭比對 14
2.2.2 基於FPGA的標頭比對 16
2.3 基於FPGA特徵字串比對 20
2.4 基於FPGA之入侵偵測系統研究 21
2.5 相關研究比較 23
第三章系統架構及設計 25
3.1 系統架構 25
3.2標頭比對電路 (Header compare circuit ) 27
3.2.1 樹狀規則標頭比對建置 28
3.2.2 規則標頭比對電路設計 31
3.3 字串比對電路(String matching circuit ) 35
3.3.1 多字串群組的建置 35
3.3.2 字串比對電路設計 37
3.4 自動化電路產生工具 38
第四章實驗與討論 41
4.1 實驗環境 41
4.2 實驗架構 42
4.3 實驗與討論 46
4.3.1 四模型架構的效能和資源利用分析 47
4.3.2 不同規則數目下效能及資源利用分析 48
4.3.3 不同規則集合分析 51
4.4 實驗小結 54
第五章結論及未來研究 55
5.1 研究結論與貢獻 55
5.2 未來研究 55
參考文獻 57

參考文獻

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[MODE] ModelSim, http://www.model.com/.
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[TIA] The ID3 Algorithm, http://www.cise.ufl.edu/~ddd/cap6635/Fall-97/Short-papers/2.htm, , access at June, 2009.

指導教授

陳奕明(Yi-Ming Chen)

審核日期

2009-7-17

推文