 |
|
|
|
以作者查詢圖書館館藏 、以作者查詢臺灣博碩士 、以作者查詢全國書目 、勘誤回報 、線上人數：65 、訪客IP：3.15.29.73
姓名 簡偉仁(Wei-jen Chien) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 應用於K頻段之低功耗低相位雜訊壓控振盪器暨Ku頻段雙模注入式除頻器之研製
(Implementations of K band Low Power and Low Phase Noise Voltage Controlled Oscillator and Ku band Dual-mode Injection Locking Frequency Divider)相關論文 檔案 [Endnote RIS 格式]
[相關文章]
[文章引用]
[完整記錄]
[館藏目錄]
[檢視]
- 本電子論文使用權限為同意立即開放。
- 已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
- 請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。
摘要(中) 本論文係應用於超寬頻(Ultra Wideband)系統之前端接收機之K頻段壓控振盪器、雙模注入式鎖頻除頻器，以TSMC 0.18-μm CMOS與TSMC 0.13-μm CMOS製程研製。
第二章介紹兩個Ka頻段的壓控振盪器(VCO)架構，使用TSMC 0.18-μm CMOS製程，其中之一的VCO主要訴求為低功耗與低相位雜訊，電路架構為電感-電容(LC)型VCO，設計負電阻的電流再生利用，將能減少功耗和低相位雜訊的需求。量測結果顯示出，操作電壓VDD為1.5 V下，功率消耗約為2.59 mW，中心振盪頻率約為12.15 GHz，可調範圍約為從12.02到12.33 GHz，相位雜訊在頻偏1 MHz時約為 -113 dBc/Hz，最大輸出功率為-4.9 dBm，優化指數為-190 dBc/Hz。另外一個VCO為設計在鎖相迴路(PLL)電路中，主要訴求為具寬頻和低電壓增益(KVCO)，電路架構為互捕式交錯耦合差動LC型 VCO，並設計2位元開關電容作為切換可調頻率範圍，量測結果顯示出，操作電壓VDD為1.8 V下，功率消耗約為7.538 mW，中心振盪頻率約為12.2 GHz，切頻開關從00 ~ 11的可調頻率範圍約為從11.8 ~ 12.61 GHz，相位雜訊在頻偏1 MHz時約為 -108 dBc/Hz，最大輸出功率為-2.48dBm，優化指數為-180.5 dBc/Hz。
第三章介紹Ku頻段VCO的架構，使用TSMC 0.13-μm CMOS製程。在LC型的共振腔中，電感和可變電容的寄生電阻將產生熱雜訊，影響整體電路相位雜訊的大小，因此，交錯耦合對的MOS，除了提供足夠的等效負電阻外，還可以利用MOS內介於閘級和基板等同一個可變電容，做為共振腔內的電容，選用MOS的高Q值基板電容替代可變電容，將有效降低相位雜訊，又可控制負阻和可變電容的大小，做為可調頻率的範圍。量測結果顯示出，電路的操作電壓於VDD為0.7V下，功率消耗為1.372 mW，中心振盪頻率約為25.6 GHz，可調範圍約為從25.47到25.98 GHz，相位雜訊在頻偏1 MHz時約為-108.8 dBc/Hz；最大輸出功率為-1.93 dBm，整體電路的功率損耗為56.8 mW，優化指數為-196.6 dBc/Hz。
第四章介紹Ku頻段的注入式鎖定除二除頻器架構，使用TSMC 0.18-μm CMOS製程。此除頻器將兩種不同注入架構，組合搭配在一起，其目的為提升兩倍頻訊號，將增加除頻器較寬的鎖頻範圍，選用LC型作共振腔，將可達到低功率的訴求。量測結果顯示出，當電路操作電壓VDD在1.8 V下，功率消耗為2.25 mW，自振頻率範圍約為從6.6 到6.9 GHz。鎖頻時相位雜訊在頻偏1 MHz時約為-137 dBc/Hz；當電壓變化從0-1.8V時，鎖頻範圍約為從12.1到14.3 GHz。最大輸出功率為-6 dBm，優值化指標為7.44。
第五章為結論，討論以上晶片優劣處，並對自己的未來期許和努力方向設計目標。
摘要(英) This thesis presents K-band voltage controlled oscillator (VCO) and injection locked frequency divider (ILFD) circuits which can apple in Ultra Wideband system of front-end receiver. The circuits were implemented in TSMC 0.13-?m and 0.18-?m CMOS technologies.
The thesis is organized as follow, Chapter 1 give the motivation and induction of system applications. Chapter 2 introduces two Ka-band VCOs topologies which were fabricated in 0.18-?m CMOS technology. The first VCO mainly targeted for low power consumption and low phase noise. The circuit topology is an LC-VCO with current reuse technique to reduce power consumption and obtain low phase noise performance. The measured oscillation central frequency is 12.15 GHz with tunable frequency range from 12.02 to 12.33 GHz. The power consumption is 2.59 mW from a power supply of 1.5 V, and -113 dBc/Hz phase noise at 1 MHz offset. The maximum output power is -4.9 dBm. The figure of merit (FOM) is high up -190.7 dBc/Hz. The second VCO is designed for wideband tuning frequency by switch capacitor array. The complementary cross-coupled differential LC-VCO was adopted. Two bits capacitance switch was used to choose the tunable frequency range. The measured oscillation central frequency is 12.2 GHz with a tunable frequency range from 11.8 to 12.61 GHz by using the 2-bit switch control (from 00 to 11). The power consumption is 7.538 mW under a power supply of 1.8 V, and -108 dBc/Hz phase noise at 1 MHz offset. The maximum output power is -2.48 dBm. The best FOM is -180.5 dBc/Hz.
Chapter 3 presents a Ku-band VCO topology which was fabricated in 0.13-?m CMOS technology. The parasitic resistance on the inductor and varactor generate thermal noise, to increase phase noise in the circuit. Therefore, cross-coupled transistors provide the sufficient negative resistance. The VCO circuit utilizes the parasitic capacitance between back and gate as a varactor which is part of LC tank to tune the oscillation frequency. This high Q bulk capacitance provides a good phase noise performance. The measured oscillation central frequency is 25.6 GHz with tunable frequency range from 25.47 to 25.98 GHz. The power consumption is 1.372 mW under a power supply of 0.6 V, and -109.9 dBc/Hz phase noise at 1 MHz offset. The maximum output power is -1.93 dBm. The best FOM is very good up to -196.6 dBc/Hz.
Chapter 4 develops a Ka-band ILFD topology which was fabricated in 0.18-?m CMOS technology. This frequency divider used two different injection paths to enhance the second harmonic which will widen the locking range ILFD. The measured free run frequency of ILFD is 6.6 GHz. The power consumption is 2.25 mW under a power supply of 1.8 V. The phase noise is -137 dBc/Hz at 1 MHz offset which VCO is under injection locked. The locking range is from 12.1 to 14.3 GHz with control voltage tuning from 0 to 1.8 V. The maximum output power is -6 dBm. The FOM is 7.44.
Finally, a brief conclusion is given in Chapter 5.
關鍵字(中) ★ 壓控振盪器
★ 注入式除頻器關鍵字(英) ★ K band
★ CMOS
★ LC-tank
★ intrinsic tuning vco
★ ILFD
★ millimeter-wave論文目次 摘要 .................................................................................................................................... i
Abstract .............................................................................................................................. iii
誌謝 ................................................................................................................................... v
目錄 ................................................................................................................................. vii
圖目錄 ............................................................................................................................... x
表目錄 ............................................................................................................................. xiii
第1章 緒論 ...................................................................................................................... 1
1.1 毫米波簡介[1] .................................................................................................... 1
1.2 研究動機 ............................................................................................................. 2
1.3 研究成果 ............................................................................................................. 3
1.4 章節簡述 ............................................................................................................. 3
第2章 壓控振盪器之相位雜訊分析 .............................................................................. 4
2.1 振盪器電路簡介 ................................................................................................. 4
2.2 振盪器基本架構 ................................................................................................. 6
2.2.1 環型振盪器 .............................................................................................. 6
2.2.2 LC型振盪器 ............................................................................................. 7
2.3 振盪器之重要參數[21]....................................................................................... 9
2.4 壓控振盪器的電路原理分析 ........................................................................... 11
2.5 相位雜訊導論[9] .............................................................................................. 13
2.5.1 Lesson相位雜訊模型 ............................................................................. 16
2.5.2 線性時變的相位雜訊模型 .................................................................... 20
2.5.3 ISF的時變效應 ...................................................................................... 29
2.6 低功耗低相位雜訊之電流再生利用壓控振盪器 ........................................... 31
2.6.1 簡介 ........................................................................................................ 31
2.6.2 設計原理 ................................................................................................ 33
2.6.3 量測結果 ................................................................................................ 36
2.6.4 比較與討論 ............................................................................................ 40
2.7 低雜訊寬頻帶之互補式交錯耦合壓控振盪器 ............................................... 41
2.7.1 簡介 ........................................................................................................ 41
2.7.2 設計原理 ................................................................................................ 42
2.7.3 量測結果 ................................................................................................ 48
2.7.4 比較與討論 ............................................................................................ 52
第3章 本質可調變容器之振幅分佈式壓控振盪器 .................................................... 54
3.1 簡介 ................................................................................................................... 54
3.2 設計原理 ........................................................................................................... 54
3.2.1 電晶體的本質電容 ................................................................................ 55
3.2.2 振幅分佈式架構和閘級偏壓位移 ........................................................ 59
3.3 量測結果 ........................................................................................................... 61
3.4 比較與討論 ....................................................................................................... 65
第4章 寬鎖頻低功率之雙模注入式鎖定除頻器 ........................................................ 67
4.1 除頻器電路簡介 ............................................................................................... 67
4.2 除頻器基本架構 ............................................................................................... 68
4.2.1 真單一相位時脈(TSPC)除頻器 ............................................................ 69
4.2.2 電流模式邏輯(CML)除頻器 ................................................................. 69
4.2.3 注入式鎖頻除頻器(ILFD) ..................................................................... 71
4.2.4 米勒(Miller)鎖頻除頻器 ....................................................................... 73
4.3 除頻器之重要參數 ........................................................................................... 75
4.4 Ku頻段雙模注入式鎖頻之除頻器(Dual-ILFD) .............................................. 76
ix
4.4.1 簡介 ........................................................................................................ 76
4.4.2 設計原理 ................................................................................................ 78
4.4.3 量測結果 ................................................................................................ 81
4.4.4 比較與討論 ............................................................................................ 86
第5章 結論 .................................................................................................................... 87
5.1 結論 ................................................................................................................... 87
5.2 未來期許與研究方向 ....................................................................................... 88
參考文獻 .......................................................................................................................... 89
參考文獻 [1]. P. Smulders, "Exploiting the 60 GHz band for local wireless multimedia access: prospects and future directions," Communications Magazine, IEEE, vol. 40, pp. 140-147, 2002.
[2]. D.B. Lesson, “A simple model of feedback oscillator noise spectrum,” in Proc.IEEE ,vol.54, issue 2,pp.329-330, Feb.1966.
[3]. A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," Solid-State Circuits, IEEE Journal of, vol. 33, pp. 179-194, 1998.
[4]. D.Ham and A.Hajimiri, “Concept and methods in optimization of integrated LC VCOs,”IEEE J.Solid-State Circuits, Vol.36, no.6, pp.896-909, Jun.2001.
[5]. Qiuting Huang, “On the exact design of RF oscillators,” IEEE Custom Integrated Circuits Conference, pp.41-44, May 1998.
[6]. W.D Cock and M. Steyaert, ”A CMOS 10 GHz voltage controlled oscillator with integrated high Q-inductor,” in Proc. IEEE Solid-State Circuit Conf., pp.498-501, Aug 2001.
[7]. T.K.K Tsang and M.N.El-Gamal, ”A high figure of merit and area-efficient low-voltage(0.7-1 V) 12 GHz CMOS VCO,” in Proc. IEEE Rad. Freq. Integr. Circuits Symp. , pp. 89-92, 2003
[8]. B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J.Solid-State Circuits, vol. 31, no. 3, pp. 1415-1424, Sep. 1996. .
[9]. A. Hajimiri and T. H. Lee, “The design of low noise oscillators.”, Kluwer Academic Publishers,1999.
[10]. Y. Seok-Ju, S. So-Bong, C. Hyung-Chul, and L. Sang-Gug, "A 1mW current-reuse CMOS differential LC-VCO with low phase noise," in Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, 2005, pp. 540-616 Vol. 1.
[11]. L. S. Culter and C. L. Searle, “Some aspects of the theory and measurement of frequency fluctuations in frequency standards,” in Proc.IEEE, vol.54, pp. 136-154, Feb. 1966.
[12]. Y. Seok-Ju, S. So-Bong, C. Hyung-Chul, and L. Sang-Gug, "A 1mW current-reuse CMOS differential LC-VCO with low phase noise," in Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, pp. 540-616 Vol. 1,2005.
[13]. S. Jin-Rong and L. Zhi-Ming, "A10-GHz 0.88-mW low-phase-noise CMOS VCO," in Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on, pp. 1063-1066 ,2009.
[14]. R. L. Bunch and S. Raman, "Large-signal analysis of MOS varactors in CMOS -Gm LC VCOs," Solid-State Circuits, IEEE Journal of, vol. 38, pp. 1325-1332, Aug. 2003.
[15]. A. Hajimiri and T. H. Lee, "Design issues in CMOS differential LC oscillators," Solid-State Circuits, IEEE Journal of, vol. 34, pp. 717-724, 1999.
[16]. S. Levantino, C. Samori, A. Bonfanti, S. L. J. Gierkink, A. L. Lacaita, and V. Boccuzzi, "Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion," Solid-State Circuits, IEEE Journal of, vol. 37, no. 8, pp. 1003-1011, Aug., 2002
[17]. Lin Jia, Jian-Guo Ma, Kiat Seng Yeo and Manh Anh Do, “9.3-10.4-GHz-band cross-coupled complementary oscillator with Low phase-noise performance,” IEEE Transactions on Microwave Theory and Techniques, vol. 52, no. 4, Apr. 2004.
[18]. Tsung-Hsien Lin and Yu-Jen Lai, “An agile VCO frequency calibration technique for a 10-GHz CMOS PLL” Solid-State Circuits, IEEE Journal of, vol. 42, no. 2, Feb., 2007
[19]. Chin-Lung Yang and Yi-Chyun Chiang, “Low phase-noise and low-power CMOS VCO constructed in current-reused configuration,” IEEE Microwave and Wireless Components letters, vol. 17 no. 2, Feb. 2008..
[20]. H. Yiping, L. E. Larson, and D. Y. C. Lie, "A low-voltage 12GHz VCO in 0.13 ?m CMOS for OFDM applications," in Silicon Monolithic Integrated Circuits in RF Systems, 2006. Digest of Papers. 2006 Topical Meeting on, 2006, p. 4 pp
[21]. Yan-Hsien Yang “The implementations of MICS band ultra low power voltage controlled oscillator and ku band local oscillator and divider,” thesis of NCU Oct.2008
[22]. S. Taeksang and Y. Euisik, "A 1-V 5 GHz low phase noise LC-VCO using voltage-dividing and bias-level shifting technique," in Silicon Monolithic Integrated Circuits in RF Systems, 2004. Digest of Papers. 2004 Topical Meeting on, 2004, pp. 87-90.
[23]. Pietro Andreani, Ali Fard, “More on the 1/f2 phase noise performance of CMOS differential-pair lc-tank oscillators,” Solid-State Circuits, IEEE Journal of, vol. 41, no. 12, Dec. 2003.
[24]. Pietro Andreani, Henrik Sjoland, “Tail current noise suppression in rf CMOS VCOs,” Solid-State Circuits, IEEE Journal of, vol. 37, no. 3, 2002.
[25]. C. Ching-Hung, L. Kung-Hao, C. Hong-Yeh, and C. Yi-Jen, "A low phase noise 26-GHz push-push VCO with a wide tuning range in 0.18-um CMOS technology," in Microwave Conference, 2006. APMC 2006. Asia-Pacific, 2006, pp. 1128-1131.
[26]. Alan W. L. Ng and Howard C. Luong, “A 1-V 17-GHz 5-mW CMOS quadrature VCO based on transformer Coupling,” Solid-State Circuits, IEEE Journal of, vol. 42, no. 9, Sep. 2007.
[27]. K. C. Kwok and John R. Long, “A 23-to-29 GHz transconductor-tuned VCO MMIC in 0.13 ?m CMOS,” Solid-State Circuits, IEEE Journal of, vol. 42, no.12, Dec. 2007.
[28]. C. Hsien-Ku, C. Hsien-Jui, C. Da-Chiang, J. Ying-Zong, and L. Shey-Shi, "A 0.6 V, 4.32 mW, 68 GHz Low Phase-Noise VCO With Intrinsic-Tuned Technique in 0.13 um CMOS," Microwave and Wireless Components Letters, IEEE, vol. 18, pp. 467-469, 2008.
[29]. L. Ja-Yol, L. Sang-Heung, K. Haecheon, and Y. Hyun-Kyu, "A 28.5-32-GHz Fast Settling Multichannel PLL Synthesizer for 60-GHz WPAN Radio," Microwave Theory and Techniques, IEEE Transactions on, vol. 56, pp. 1234-1246, 2008.
[30]. U. Singh and M.M. Green, “High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz,” IEEE J. Solid-State Circuits ,vol.40, no. 8,pp. 1658-1661,Aug. 2005.
[31]. T.-C. Lee and Y.-C Huang, “A Miller divider based clock generator for MBOA – UWB application,” in VLSI Circuits Symp. Tech. Dig., pp. 34-37, Jun. 2005.
[32]. H. Wu and A. Hajimiri, “A 19 GHz 0.5mW 0.35μm CMOS frequency divider with shunt-peaking locking-range enhancement,” in IEEE Int. Solid-State Circuit Conf., pp. 412-413,417, Feb. 2001.
[33]. S.-H. Lee, S.-L Jang, J.-F. Lee, Y.-H. Chung and H.-M.Chen “A LC-tank injection locked frequency divider with complementary structure,” in VLSI Design, Automation and Test, VLSI-DAT, pp. 1-4, 2007.
[34]. P. Adreanj and H. Sjoland, “A 2.2 GHz CMOS VCO with inductive degeneration noise suppression,” in Proc. IEEE Custom Integr. Circuits Conf., pp.197-200, San Diego, CA, May 2001.
[35]. M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” in IEEE J.Solid-State Circuits, vol. 39, no. 7, pp. 1170-1174, Jul. 2004.
[36]. R. L. Bunch and S. Raman, “Large-signal analysis of MOS varactors in CMOS –Gm LV VCOs,” IEEE J. Solid-State Circuits, vol.38, pp. 1325-1332,Aug. 2003.
[37]. B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE J.Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, Sep. 2004.
[38]. Jri Lee and B. Razavi, “A 40-GHz frequency Divider in 0.18-μm CMOS Technology,” IEEE Journal of Solid-State Circuit, vol. 39, no. 4, Apr. 2004.
[39]. S.-L Jang, C.-F Lee and W.-H Yeh, “A divider-by-3 injection Locked frequency divider with single-ended input,” IEEE Microwave and Wireless Components, vol. 18, no. 2, Feb. 2008.
[40]. Y.-H Chuang, S.-H Lee, R.-H Yen, S-L Jang, J.-F Lee and M.-H Juang, “A wide locking range and low voltage CMOS direct injection-locked frequency divider,” IEEE Microwave and Wireless Components, vol. 16, No. 5, May 2006.
[41]. S.-H Lee, S.–J Jang, “A low power injection locked LC-tank oscillator with current reused topology,” IEEE Microwave and Wireless Components, vol. 17, no. 3, Mar. 2007.
[42]. C.-F Lee, S.-L Jang, and M.-H. Juang, “A wide locking range differential colpitts injection locked frequency divider,” IEEE Microwave and Wireless Components, vol. 17, no. 11, Mar. 2007.
[43]. S.-L Jang, J.-C Luo, C.-W Chang, C.-F Lee and J.-F Huang, “LC-tank Colpitts injection-locked frequency divider with even and old modulo,” IEEE Microwave and Wireless Components, vol. 19, no. 2 , Feb. 2009.
[44]. S.L Jange, and C.-F Lee, “A wide locking range LC-tank injection-locked frequency divider,” IEEE Microwave and Wireless Components,vol. 17, no. 8, Aug. 2009.
[45]. T.-N. Luo and Yi-Jan Emery Chen, “A 0.8-mW 55-GHz dual-injection-locked CMOS frequency divider.” IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 3, Mar. 2008.
[46]. H.-K Chen, D.-C Chang, Y.-Z Juang and S.-S Lu, “A 30-GHz wideband low-power CMOS injection-locked frequency divider for 60-ghz wireless-lan,” IEEE Microwave and Wireless Components, vol. 18, no. 2, Feb. 2008.
[47]. Chung-Yu Wu and Chi-Yao Yu, “Design and analysis of millimeter-wave direct injection-locked frequency divider with large frequency locking range,” IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 8, Aug. 2007.
[48]. L. Ja-Yol, L. Sang-Heung, K. Haecheon, and Y. Hyun-Kyu, “A 28.5-32-GHz fast settling multichannel PLL synthesizer for 60-GHz WPAN radio,” Microwave Theory and Techniques, IEEE Transactions on, vol. 56, pp. 1234-1246, 2008.
[49]. 梁可俊, “Impulse sensitivity function analysis for phase noise characteristic of voltage controlled oscillator and implementation of K-band different low noise amplifier,” 碩士論文, 中央大學. 2007
[50]. 陳憲瑞, “The Implementations on Wireless System of Wide-Band Front-End Receiver, Frequency Synthesizer, and V Band Frequency Divider,” 碩士論文, 中央大學.2007
[51]. 劉深淵和楊清淵, “鎖相迴路,” 滄海書局,2006.
[52]. Behzad Razavi, “Design of analog CMOS integrated circuits,” 滄海書局,2005.
指導教授 邱煥凱(Hwann-Kaeo Chiou) 審核日期 2010-1-14 推文 plurk
funp
live
udn
HD
myshare
netvibes
friend
youpush
delicious
baidu
網路書籤 Google bookmarks
del.icio.us
hemidemi
facebook
twitter
google
reddit