以數位信號處理器實現H.264/SVC解碼器及其最佳化演算法設計

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姓名

林黃淳(Huang-Chun Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

以數位信號處理器實現H.264/SVC解碼器及其最佳化演算法設計
(The Realization and Optimization Technique for H.264/SVC decoder on Digital Signal ProcessorPlatform)

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摘要(中)

隨著多媒體的應用越來越多，要使一個多媒體視訊壓縮影片符合不同的多媒體媒
介，例如：車用通訊、手機影音、電腦和HD 電視等多媒體設備，則多媒體編解碼器需
要更符合這些硬體配備的需求來進行視訊的編解碼，為了因應這種需求，ITU-T Video
Coding Experts Group基於H.264/AVC發展了延伸於H.264編解碼標準H.264/SVC[1]，
H.264/SVC 編解碼標準針對了撥放影格率、解析度、畫面品質精細度這三種不同的型態
來進行可伸縮視訊編碼，編碼後的視訊位元流可以解碼成符合不同解析度、網路條件和
硬體能力的多媒體設備的影片資訊。然而，這種編解碼技術其模組複雜度相當的高，而
降低其複雜度在現今乃是一個非常重要的議題。
本篇論文利用數位訊號處理器實現H.264/SVC解碼器，而在H.264/SVC解碼器方面
是以參考軟體JSVM9.16[2]來移植於數位處理器平台DM6437[3]。我們經由計算各種不
同可伸縮功能Temporal、Spatial、SNR 及Combine 模式來進行其分析，針對分析出來
的結果來進行各模組的最佳化。此篇論文提出了在反離散餘弦轉換模組(Inverse
discrete cosine transform)及內插放大模組(Interpolation Up-sampling)這兩個部
份的基於DM6437的最佳化方法，並分別達到10.7倍和平均12.29倍的效能提升。除此
之外利用開發環境的工具、記憶體的規劃及一些特殊指令來最佳化我們的H.264/SVC解
碼器系統使其在Combine的模式下得到5.79 倍的效能提升。
在本篇最後，會闡述一個可伸縮視訊解碼撥放器完整的系統實現在DM6437 開發平
台上，此系統利用網路由電腦傳輸壓縮過的視訊位元流將其傳送到DM6437 開發板進行
資料的解壓縮，解壓縮過後的資料並以液晶螢幕顯示出來，在可伸縮的功能實現上，我
們利用開發平台的指撥開關來調整Temporal、Spatial、SNR 和Combine 等模式，而此
功能的實現還需嵌入一個位元流擷取器(Bitstream Extractor)方得實現。

摘要(英)

The video coding technique has been extensively applied in many scenarios of our daily
life. For example: vehicle electronics applications, mobile phone, computer, high-definition
television ...etc. To support such various applications, a versatile video coding scheme is
essential. Therefore, ITU-T Video Coding Experts Group has developed a video standard
H.264/SVC [1], an extension of H.264/AVC [7]. It can provide the bitstream adaption to fit in
with different resolution, network condition and hardware capability. The H.264/SVC
includes three types of scalability: temporal, spatial and SNR scalability. However, the
complexity of H.264/SVC decoder is very high. For this reason, how to reduce the complexity
of H.264/SVC is very important issue.
In this thesis, we realize the H.264/SVC decoder with Texas Instrument DM6437 DSP
platform. This work transplants the reference software JSVM9.16 [2] to the DSP platform
DM6437 [3]. We separately analyze the complexity of H.264/SVC decoder in for temporal,
spatial, SNR and Combine scalability. According to the analysis result, we optimize each
module of H.264/SVC decoder. This thesis proposed two optimization methodologies in
inverse discrete cosine transform (IDCT) module and up-sampling module. With both
optimizations, the performance of IDCT and up sampling module can be increased as high as
10.7x and 12.29x, respectively. Besides, we also utilized the Code Composer Studio (CCS) to
draw up the memory mapping and explored some special intrinsic instructions to improve the
decoding performance. The overall decoder system can speed up 5.79x on average.
Finally, we will show a complete H.264/SVC decoder system. It is implemented in
DM6437 DSK. This system received the bitstream through network and decoded the
bitstream to obtain video information. Furthermore, the bitstream extractor is also
transplanted into this system. The decoded video information is displayed on LCD monitor.
To switch scalability function, we applied DIP switchs to separately enable temporal, spatial,
SNR, and combine scalability.

關鍵字(中)

★ 餘弦離散轉換
★ 可調式解碼器
★ 數位訊號處理器
★ 視訊解碼器

關鍵字(英)

★ DCT
★ Decoder
★ H.264/SVC
★ Digital signal processor

論文目次

摘要 ..................................................................... I
ABSTRACT .............................................................. II
誌謝 .............................................................. III
目錄 .................................................................... IV
圖目錄 .................................................................. VI
表目錄 ................................................................ VIII
第一章緒論 .............................................................. 1
1.1動機與背景 ................................................................................................................ 2
1.2數位訊號處理器 ......................................................................................................... 3
1.3實驗係數 .................................................................................................................... 4
1.4論文組織架構 ............................................................................................................ 5
第二章 H.264/SVC 可伸縮視訊編解碼標準介紹 ................................ 6
2.1 H.264/SVC背景 ......................................................................................................... 7
2.2.H.264/SVC的架構 ..................................................................................................... 8
2.2.1 H.264/SVC編碼器其架構 ................................................................................. 8
2.2.2 H.264/SVC解碼器架構 ..................................................................................... 9
2.3 時域上的可伸縮性功能(TEMPORAL SCALABILITY) ................................................. 10
2.4空間域的可伸縮性功能(SPATIAL SCALABILITY) ...................................................... 11
2.4.1 層間畫面內預測(Inter-layer Intra Prediction) ................................................ 12
2.4.2 層間移動預測(Inter-layer Motion Prediction) ................................................ 14
2.4.3 層間殘值預測(Inter-layer Residual Prediction) .............................................. 15
2.5訊雜比的可伸縮性功能(SNR SCALABILITY)........................................................... 15
2.5.1 粗顆粒雜訊比可伸縮性(Coarse-Grain Scalability)........................................ 16
2.5.2中顆粒雜訊比可伸縮性(Median-Grain Scalability) ........................................ 16
2.6總結 .......................................................................................................................... 16
第三章數位訊號處理平台DM6437介紹 ...................................... 17
3.1 數位訊號處理器平台 .............................................................................................. 18
3.2 DM6437 訊號處理平台 .......................................................................................... 19
3.3 DM6437 數位訊號處理器 ......................................................................................... 20
3.4 C64X VELOCITI.2 EXTENSIONS技術 ......................................................................... 21
3.4.1 封包資料的處理(Packed data processing) ..................................................... 21
3.4.2特殊用途的指令 ............................................................................................... 23
3.4.3對C64x原有架構的加強 ................................................................................. 23
3.5 快取架構.................................................................................................................. 24
3.6 增強的直接記憶體存取器(ENHANCED DIRECT MEMORY ACCESS CONTROLLER) ..... 25
3.7 TI DSP 開發環境 ..................................................................................................... 26
3.8 系統開發流程 .......................................................................................................... 31
第四章 H.264/SVC 解碼器之複雜度分析 ..................................... 32
4.1效能分析簡介 .......................................................................................................... 33
4.2移植問題解決 .......................................................................................................... 33
4.2.1 MEMORY ALIGNMENT的問題： .................................................................. 33
4.2.2 資料型態問題與標準函式庫問題 ................................................................... 34
4.3 效能分析設定 .......................................................................................................... 36
4.4 各可伸縮功能的效能剖析 ....................................................................................... 39
第五章 H.264/SVC 解碼器之優化與複雜度降低 ............................... 44
5.1 優化與降低複雜度介紹 .......................................................................................... 45
5.2 基本的最佳化方法 .................................................................................................. 46
5.2.1 使用編譯器最佳化系統 .................................................................................. 46
5.2.2 移除不需要的判斷及函式............................................................................... 46
5.2.3 使用內聯函數(Intrinsic) ............................................................................. 48
5.3 反離散餘弦轉換之最佳化 ....................................................................................... 51
5.3.1反離散餘弦轉換之原理與剖析 ........................................................................ 51
5.3.2反離散餘弦轉換之最佳化瓶頸 ........................................................................ 53
5.3.3反離散餘弦轉換之最佳化................................................................................ 53
5.4 內插放大模組之最佳化 .......................................................................................... 59
5.4.1內插放大模組之頻頸與最佳化 ........................................................................ 61
第六章 H.264/SVC 解碼器系統之實現 ....................................... 66
6.1 最佳化之H.264/SVC解碼器模擬結果 ................................................................... 67
6.2 H.264/SVC解碼器撥放系統的架構 ....................................................................... 67
第七章結論 ............................................................. 71
REFERENCE ............................................................... 73

參考文獻

[1] ITU-T and ISO/IEC JTC 1, “Advanced Video Coding for Generic Audiovisual Services,”
ITU-T Recommendation H.264 and ISO/IEC 14496-10 (MPEG-4 AVC), Version 8 (including
the SVC extension): Consented in July 2007.
[2] Jerome Vieron, Mathias Wien Heiko Schwarz, “ Draft reference software for
SVC,“ ISO/IEC MPEG & ITU-T VCEG, JVT-AC203, October, 2008.
[3] Texas Instruments, “TMS320DM6437 Digital Media Processor,” Literature number:
SPRS345D, JUNE 2008.
[4] T. Wiegand, G. J. Sullivan, G. Biontegaard, and A. Luthra, “Overview of the H.264/AVC
Video Coding Standard,” IEEE Transactions on Circuit and System for VideoTechnology,
VOL. 13, Issue 7, pp. 560-576, Jul. 2003.
[5] Heiko Schwarz, Detlev Marpe,, and Thomas Wiegand, “Overview of the Scalable Video
Coding Extension of the H.264/AVC Standard,” Ieee Transactions On Circuits And Systems
For Video Technology, VOL. 17, pp. 1103-1120, Sep. 2007.
[6] Heiko Schwarz, Mathias Wien, “The Scalable Video Coding Extension of the H.264/AVC
Standard,” IEEE Signal processing Magazine, pp. 135-144, March 2008.
[7] “Advanced Video Coding for Generic Audiovisual Services, “ ITU-T Rec.H.264 and
ISO/IEC 14496-10 (MPEG-4 AVC), ITU-T and ISO/IEC JTC 1, Version 1: May 2003,
Version 2: May 2004, Version 3: Mar. 2005, Version 4: Sept. 2005, Version 5 and Version 6:
June 2006, Version 7: Apr. 2007, Version 8 (including SVC extension): Consented in July
2007.
[8] Heiko Schwarz, Detlev Marpe, and Thomas Wiegand, “ANALYSIS OF HIERARCHICAL
B PICTURES AND MCTF,” in Proc. ICME, Toronto, ON, Canada, Jul.2006, pp. 1929–1932.
[9] Texas Instruments, “Code Composer Studio User’s Guide,” Literature number:
SPRU328B, February 2000.
[10] Texas Instruments, “TMS320DM6437 DVDP Getting Started Guide,” Literature number:SPRUEV6, July 2007.
[11] Texas Instruments, “TMS320C64x/C64x+ DSP CPU and Instruction Set Reference
Guide,” Literature number: SPRU732G, February 2008.
[12] Jeremiah Golston, David Hoyle, Vishal Markandey, Jagadeesh Sankaran, Joe Zbiciak,
“C64x VelociTI.2 extensions support media-rich broadband infrastructure
and image analysis systems, ” Media processors. Conference, San Jose CA , ETATS-UNIS
(23/01/2001) 2001 , vol. 4313, pp. 1-10.
[13] Texas Instruments, “TMS320C64x+ DSP Cache User's Guide,” Literature number:
SPRU862B, February 2009.
[14] Texas Instruments, “TMS320DM643x DMP Enhanced Direct Memory Access (EDMA3)
Controller,” Literature number: SPRU987A, March 2008.
[15] Texas Instruments, “TMS320C6000 DSP/BIOS 5.32 Application Programming Interface
(API) Reference Guide,” Literature number: SPRU403O, September 2007.
[16] Texas Instruments, “DSP/BIOS, RTDX and Host-Target Communications,” Literature
number: SPRA895, February 2003.
[17] Texas Instruments, “TMS320C6000 Optimizing Compiler User’s Guide,” Literature
number: SPRU187L, May 2004.
[18] Texas Instruments, “TMS320C6000 Programmer’s Guide,” Literature number:
SPRU198I, March 2006.
[19] Texas Instruments, “TMS320C6000 Assembly Language Tools v 6.0 Beta User's guide,”
Literature number: SPRU186P, October 2006.
[20] Joohyun Lee, Gwanggil Jeon, Sangjun Park, Taeyoung Jung, and Jechang Jeong, “SIMD
Optimization of the H.264/SVC decoder with efficient data structure,” in Proc. ICME 2008,
Hannover, Germany, June 2008.
[21] Sung D.Kim, Jeong H.Lee, Jung M. Yang, Myung H. Sunwoo, and Sung K. Oh, “Novel
instructions and their hardware architecture for video signal processing ,” in Proc. ISCAS
2005, Kobe, Japan, May 2005.

指導教授

蔡宗漢(Tsung-Han Tsai)

審核日期

2009-11-24

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