考慮電源完整性與輸出/入埠限制之積體電路設計配置方法

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姓名

呂昭宏(Chao-Hung Lu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

考慮電源完整性與輸出/入埠限制之積體電路設計配置方法
(VLSI Design Planning with Power Integrity and I/O Constraints)

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摘要(中)

超大型積體電路設計日益複雜，加上奈米效應使得晶片與封裝的設計變得更加困難，因此電子設計自動化產品也必需不斷的進步以符合時代的需求。由於市場需求，電路需擁有較高的效能與較低的供應電壓等特性，且因所需的輸入/輸出埠不斷增加造成封裝設計上困難度不斷的增加。在此論文中，我們提出了幾個新的佈局規劃與配置方法。這些方法不只可以解決電源雜訊上的問題，還可以考慮封裝設計以及堆疊晶片的設計問題。
關於電源雜訊中的同時性邏輯轉換雜訊問題方面，我們採用了一個二階式技術:佈局規劃與電容插入。首先利用佈局規劃的方法盡可能抑制雜訊，之後再藉由去耦合電容插入的方法，來改善雜訊問題。因佈局規劃與電容插入的方法均有考慮到整體面積的問題，因此最後因為改善雜訊而付出的面積代價是非常小的。關於電源雜訊中的電壓降雜訊與封裝設計方面，我們採用了一個推算輸入/輸出埠排序的方法來解決此一問題，主要是因為輸入/輸出埠的排序會影響到晶片核心的電壓降雜訊與封裝繞線複雜度。雖然現今的輸入/輸出埠數量非常的大，但我們的推算方法只需要花費O(n)的時間就可推算出最適的位置。另外，堆疊設計是最能有效提供高效能晶片的設計方法，在論文中我們提出了一個分割方法來有效配置輸入/輸出埠的位置，且此一方法能同時考量連接元件數量。最後再用佈局規劃方法來改善對於最後整體晶片面積的影響。

摘要(英)

In modern VLSI deigns, manufacturing issues have complicated the designs of chips as well as packages. Moreover, due to the requirement of the market, modern circuits have higher functionality, lower supply voltage and more I/Os. These conditions increase complexity of chip designs. In this dissertation, we present some I/O plan and floorplan methods to solve these problems. They cannot only be applied to mitigate the power supply noise in the core, but also can consider the package designs, and stacking IC designs.
For the simultaneous switching noise, our method adopts a two-stage technique of the floorplan followed by the decoupling capacitance (decap) insertion. In the floorplan, the area and noise are evaluated to find a noise-driven floorplanning result. Then, we use a noise-driven decap planning approach to inserting minimal decaps into a floorplan. For IR-drop and the packages issues, we adopt a finger/pad assignment method to solve these problems. Our finger/pad assignment is a two-step method: we first solve the package design problem, then try to minimize IR-drop by switching finger/pad locations. In addition, since stacking IC is promising to the development of a high-performance IC, in this dissertation, we propose a partition approach to minimizing the 3D-vias and balancing the I/O number for each tier in stacking IC. Finally, we perform a floorplanning to show the importance of the aspect-ratio factor in stacking IC.

關鍵字(中)

★ 輸出/入埠配置
★ 電源完整性

關鍵字(英)

★ I/O Planning
★ Power Integrity

論文目次

Chapter 1 Introduction - 1 -
1.1 Trends in VLSI - 1 -
1.2 Stacking IC Advantage and Technology - 2 -
1.3 Power Integrity Impacts in Chip Design - 6 -
1.4 Impacts of I/O Pad Location in 2-D and Stacking ICs - 7 -
1.5 Dissertation Organization - 8 -
Chapter 2 Effective Decap Insertion in Area-Array I/O Architecture - 9 -
2.1 Overview of Decap Insertion - 9 -
2.2 Power Delivery and Signal Integrity Issues - 12 -
2.2.1 Power Delivery Model and Noise Estimation - 12 -
2.2.2 Decap Budgeting in Area-Array Architecture - 14 -
2.2.3 Problem Formulation - 15 -
2.3 Minimal Decap Allocation in Power Supply Noise Aware Floorplanning - 15 -
2.3.1 O-Tree Based Power Supply Noise Aware Floorplanning - 16 -
2.3.2 Feasible Region for Decap Allocation - 22 -
2.3.3 Identification of Space Priority for Decap Insertion - 24 -
2.3.4 Decap Compensation for Voltage Drop in of Power Network - 25 -
2.4 Experimental Results - 28 -
Chapter 3 Package Routability- and IR- Drop-Aware Finger/Pad Assignment - 32 -
3.1 Overview of Package Design Methods - 32 -
3.2 Congestion and IR-Drop Violation Minimization in Finger/Pad Planning - 36 -
3.2.1 Architecture and Routing of BGA Package in 2-D IC - 37 -
3.2.2 Architecture and Influence of BGA Package in Stacking ICs - 38 -
3.2.3 The Impact of Finger/Pad Locations on Wire Congestion - 38 -
3.2.4 The Impact of Finger/Pad Locations on IR-Drop Violation - 39 -
3.2.5 Problem Formulation - 41 -
3.3 Congestion-driven Finger/Pad Assignment with IR-Drop Improvement - 42 -
3.3.1 Congestion-driven Finger/Pad Assignment - 42 -
3.3.2 Finger/Pad Exchange of 2-D and Stacking ICs for IR-Drop and Bonding Wire Improvement - 48 -
3.4 Experimental Results - 51 -
Chapter 4 Design Planning with 3D-Via Optimization in Stacking IC - 55 -
4.1 Overview of Our Partition Method - 55 -
4.2 Stacking IC Models and Design Flow - 57 -
4.2.1 3D-Via and Stacking IC Models - 58 -
4.2.2 Design Flow of Alternative Stacking IC - 58 -
4.2.3 The Impact of I/O Location in Alternative Stacking IC - 61 -
4.2.4 Problem Formulation - 62 -
4.3 I/Os and Modules Planning with Minimal 3D-Via Number in Alternative Stacking ICs - 63 -
4.3.1 Global Planning for I/Os and Modules - 63 -
4.3.2 I/O Allocation by Congestion-driven Planning and Iterative Refinement - 65 -
4.4 Experimental Results - 67 -
Chapter 5 Concluding Remarks and Future Works - 71 -
Reference - 74 -

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指導教授

劉建男、陳宏明
(Chien-Nan Liu、Hung-Ming Chen)

審核日期

2010-1-26

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