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姓名 何建宏(Chien-hung Ho) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 有效尋找角落分析與蒙地卡羅模擬之最差情形的方法
(Efficient Worst Case Identification Method for PVT Corner Analysis and Monte Carlo Simulation)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 現今的製程已經達到奈米層級,在元件(device)上因製造(manufacture)時所產生的變異(variation)隨處可見,而這些變異大致上可區分為全域變異(global variation)及區域變異(local variation)兩種,當製程變異造成電路效能變化過大時,可能會造成電路設計失效,而導致晶片製造良率(yield)下降,因此,在晶片正式下線前需要對這些變異進行分析,以保證晶片出貨的品質。
在全域變異的考量上,結合製程(process)、電源(voltage)、溫度(temperature)之極端情況的角落分析(Corner Analysis)是廣泛被運用的,但在現今的製程中,完整的角落分析需要經過數百或數千個角落的模擬,太過耗時而變得不實用。而在區域變異方面,由於其變因相當的多,常見的做法是將各個變因以統計的型式表示,再使用蒙地卡羅(Monte Carlo)模擬來分析,若要得到較準確的統計結果,也需模擬數千筆以上的樣本(samples),亦是相當耗時的過程。
在本論文中提出了一個快速尋找電路最差角落的方法,可以分析出幾個合適的角落進行模擬,而不必跑完所有角落,有效提升了角落分析的效率。該分析的結果也可以用來篩選蒙地卡羅模擬的樣本,只有可能性較高的樣本才會真正進行電路模擬,大大節省了蒙地卡羅分析的模擬時間。從幾個不同電路的實驗結果中可以看出,本論文所提出的方法確實都可以用少量的樣本模擬找到電路效能最糟的情況,大大提升了製程變異分析的效率以及準確度。摘要(英) As the technology goes to nanometer scale, process variations in manufacturing become more and more significant. Those variations can be roughly classified as global variation and local variation. If the process variation changes circuit performance too much, it may cause the design fail to meet its specifications and decease the design yield. In order to guarantee the chip quality, analyzing global/local variations before manufacturing is essential.
For global variations, process-voltage-temperature (PVT) corners that combine the extreme cases of those factors are widely used to check the performance bound. However, in the advanced technology node, the number of PVT corners is growing exponentially. Exhaustive simulation of PVT corners is not practical for now. For local variations, Monte Carlo simulation is often used to handle the huge variable numbers by using the statistical model of each variable. However, accurate statistical results often require thousands of samples, which is also a time-consuming process to run thousands of circuit simulations.
This thesis proposes an efficient algorithm to find the worst-case corner of circuits. Instead of full corner simulation, only a few relevant corners are extracted to run circuit simulation, which greatly improves the efficiency of corner analysis. In addition, the proposed analysis can also help to choose the samples with higher possibility to be worst case in Monte Carlo simulations. Significant speedup can be obtained for Monte Carlo simulations because only a few samples are required to be simulated. According to the experimental results on several circuits, the proposed approach finds the worst cases in all circuits with very few samples, which greatly improves the efficiency and accuracy of process variation analysis.關鍵字(中) ★ 找尋最差效能
★ 角落分析關鍵字(英) ★ Worst Case Identification
★ PVT Corner Analysis論文目次 摘要................................................................I
Abstract............................................................II
致謝..............................................................III
目錄...............................................................IV
圖目錄............................................................VII
表目錄..............................................................X
第一章 緒論.........................................................1
1-1 研究動機 ........................................................................................................1
1-2 角落分析相關研究 ........................................................................................3
1-2-1 猜測最差情形方式 (Guess Worst Case) ...........................................3
1-2-2 一次一因子法 (One-Factor-at-a Time)..............................................4
1-2-3 析因抽樣 (Factorial Sampling)..........................................................5
1-2-4 完全析因抽樣 (Full Factorial Sampling) ..........................................7
1-3 蒙地卡羅模擬法 ............................................................................................8
1-4 論文結構 ........................................................................................................9
第二章 背景知識....................................................10
2-1 變異種類 (variation type) ...........................................................................10
2-2 參數變異帶來的影響 ..................................................................................11
2-3 模型組方法 (modelset approach) ...............................................................12
2-4 PVT 角落分析 (PVT Corner Analysis)........................................................13
2-5 蒙地卡羅分析統計形區域變異 ..................................................................15
第三章 有效尋找角落分析與蒙地卡羅模擬之最差情形的方法..............16
3-1 最差效能 PVT 角落分析 (Worst PVT Corner Analysis) ...........................16
3-1-1 因子影響量計算 (Factor Weight Calculation)................................18
3-1-2 初始最差情形候選角落...................................................................19
3-1-3 因子相關性預估 (Correlation Prediction).......................................20
3-1-4 相關係數矩陣 (Correlation Coefficient Matrix).............................22
3-1-5 更新最差情形候選角落...................................................................23
3-2 蒙地卡羅區域變異分析 ..............................................................................25
3-2-1 蒙地卡羅因子影響量.......................................................................26
3-2-2 因子影響量在蒙地卡羅模擬中的意義...........................................28
3-2-3 計算樣本權重...................................................................................29
3-2-4 因子化簡...........................................................................................31
3-2-5 模擬及結束模擬...............................................................................31
第四章 實驗結果與分析..............................................33
4-1 6T 靜態記憶體元件 (6T SRAM bit cell) ....................................................34
4-1-1 實驗環境...........................................................................................34
4-1-2 實驗結果...........................................................................................35
4-2 記憶體存取電路 (Memory I/O) .................................................................36
4-2-1 實驗環境...........................................................................................36
4-2-2 實驗結果...........................................................................................37
4-3 兩級式運算放大器 (Two-stage operational amplifier) ..............................38
4-3-1 實驗環境...........................................................................................39
4-3-2 實驗結果...........................................................................................40
4-4 佈局後兩級式運算放大器 (Post layout Two-stage operational amplifier)41
4-5 角落分析實驗總結 ......................................43
4-6 兩級式運算放大器區域變異分析 .......................44
4-6-1 實驗環境................................44
4-6-2 實驗結果................................44
4-6-3 實驗結果討論................................48
第五章 結論.....................................49
第六章 參考文獻.....................................50參考文獻 [1] C. Guardiani, M. Bertoietti, N. Dragone, M. Malcotti, P. McNamara, "An effective DFM strategy requires accurate process and IP pre-characterization," in Proceedings Design Automation Conference, pp.760,761, June 2005
[2] R. L. Mason, R. F. Gunst, J. L. Hess, Statistical Design and Analysis of Experiments, Wiley, 2003
[3] V. Czitrom, “One-Factor-at-a-Time v.s. Designed Experiments,” American Statistical Association, 1999
[4] Synopsys, Hspice user guide:Simulation and Analysis, pp. 773-774, December 2010
[5] T. McConaghy, K. Breen, J. Dyck, A. Gupta, Variation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide, Springer, 2013
[6] T. Karnik, S. Borkar, V. De, “Sub-90 nm technologies and opportunities for CAD,” International Conference on Computer-Aided Design, pp. 203-206, 2002
[7] T. Karnik, S. Borkar, V. De, “Parameter variations and Impact on Circuits and Microarchitecture,” Design Automation Conference, pp. 338-342, 2003
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[9] Liyi Xiao, Chang Liu, Yu Sun, “A novel adpative reverse body technique to minimize stanby leakage power and compensate process and temperature variations,” Cross Strait Quad-Regional Radio Science and Wireless Technology Conference, pp. 1565-1568, 2011
[10] S. Kirkpatrick, C. D. Gelatt Jr., and M. P. Vecchi, “Optimization by Simulated Annealing”, Science, vol. 220, no. 4598, pp. 671-680, May 1983.
[11] Agilent Inc, “Introduction of Corner Modeling ”, http://edocs.soco.agilent.com/display/iccap2010/Introduction+to+Corner+Modeling
[12] Solido Design Automation Inc, “Variation-Aware Custom IC Design: Improving PVT and Statistical Maximum Yield at the Performance Edge ”
[13] Solido Variation Designer cand Cadence Virtuoso Custom IC Platform, “Fast, Accurate Variation-Aware Custom IC Design”
[14] Solido Design Automation Inc, Synopsys Inc, “De-Risking Variation-Aware Custom IC Design with Solido Variation Designer and Synopsys Hspice”
[15] Solido Design Automation Inc, “High-Sigma Monte Carlo for High Yield and Performance Memory Design”
[16] Semiconductor Industry Associate, International Technology Roadmap
for Semiconductors, 2013
[17] David Freedman; Robert Pisani, Roger Purves. Statistics. Norton & Company. 1998: 148. ISBN 9780393960433
[18] V.Veetil, K. Chopra, D. Blaauw, D. Sylvester, “Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions, vol.30, no.6, pp.852,865, June 2011
[19] L. Dolecek, M. Qazi, D. Shah, A. Chandrakasan, , "Breaking the simulation barrier: SRAM evaluation through norm minimization," Computer-Aided Design,ICCAD,IEEE/ACM International Conference pp.322,329, 10-13 Nov. 2008
[20] 盧冠睿, “考慮製程、壓力、溫度的可適應性最差情形確認方法 ,”國立中央大學電機工程研究所碩士論文,July 2013指導教授 劉建男(Chien-nan Liu) 審核日期 2014-8-27 推文 plurk
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