使用波動數位濾波器與非線性MOS模型的類比電路模擬平台

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姓名

韓易學(Yi-Syue Han) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

使用波動數位濾波器與非線性MOS模型的類比電路模擬平台
(A Simulation Platform for Analog Circuits Using Wave Digital Filters and Nonlinear MOS Model)

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摘要(中)

目前的系統晶片(System-on-Chip, SOC)設計中，通常會同時包含數位電路和類比電路，因此類比/混合訊號(Analog/mixed-signal, AMS)電路的系統驗證在整個設計流程中更顯重要。但目前並沒有完整的AMS仿真器來支援整個系統驗證，因此，在這篇論文中，我們利用波動數位濾波器(Wave Digital Filter, WDF)的原理，直接以數位電路來模擬類比電路的行為。此方法使用入射波與反射波的方式描述電路特性，把連續訊號的類比電路轉成離散的數位等效電路，因此每個電路元件都可以一對一對映至數位系統中。
然而，在傳統的WDF原理之中，非線性元件無法有直接對映的方法，為了處理非線性的MOS元件，本論文提出一種WDF的非線性模型，並且使用查表法來提升非線性模型的準確度，在各種不同的製程與應用時，只需更改表格的內容，就能輕易應用在不同的製程。並且我們開發出一個WDF的軟體驗證環境，可以對SPICE netlist轉成WDF netlist進行功能模擬，並且與電晶體層級的模擬作比對，確認轉換過程的正確性，還可以讓之後開發不同的非線性元件模型時，能夠快速地評估各種模型的正確性與收斂度，用來減少未來製作硬體時的除錯時間。

摘要(英)

Generally, it contains digital and analog circuits in current system-on- chip (SOC) design. It is very important to have a complete AMS system verification environment to speed up the design. Especially, there is not any AMS emulator commercially available at this moment. Therefore, in the thesis, we adopt Wave Digital Filter theory to simulate analog circuits by using digital elements. This method uses incident and reflected waves to describe circuit to that of the discrete digital circuit. Every analog element can be mapped into digital system one by one.
However, there is no winning solution to map non-linear element directly in conventional wave digital theory. To deal with nonlinear MOSFET element, the thesis proposes a WDF-base nonlinear model. In addition, we use lookup table approach to promote accuracy of the nonlinear model that is easy to handle variety of processes and applications. A software verification environment is also developed to simulate WDF netlist and the SPICE netlist to check the accuracy of the transformation. For newly developed different nonlinear element models, we can quickly check the accuracy and the convergence rate of each model too. It can reduce dramatically the hardware debug time in the future design iteration.

關鍵字(中)

★ 波動數位率波器
★ 非線性MOS模型

關鍵字(英)

★ wave digital filters
★ nonlinear MOS model

論文目次

摘要 i
Abstract ii
目錄 iv
圖目錄 vi
表目錄 viii
1 第一章、緒論 1
1-1 研究動機 1
1-2 相關研究 3
1-2-1 場列式可程式類比陣列(FPAA) 3
1-2-2 可程式化類比元件陣列(PANDA) 5
1-2-3 硬體加速電路模擬分析 6
1-3 論文結構 7
2 第二章、背景知識 9
2-1 波動數位濾波器仿真器之完整流程圖 9
2-2 波動數位濾波器的背景知識(Wave Digital Filter) 10
2-2-1 數位濾波器模型 10
2-2-2 波動數位濾波器模型 12
2-2-3 配線器(Adaptor) 16
2-2-4 非線性元件 18
2-3 線性等效電路 19
2-4 問題定義 21
3 第三章、非線性MOS模型 22
3-1 非線性MOS元件 22
3-2 非線性MOS的建表 25
3-3 消除非線性元件在WDF中的問題 28
3-4 WDF軟體驗證模擬平台 32
4 第四章、實驗結果 35
4-1 模擬共源放大器 35
4-2 模擬疊接共源放大器(cascade) 39
5 第五章、結論與未來工作項目 44
6 參考文獻 45

參考文獻

[1] M. Vertregt, “The analog challenge of nanometer CMOS,” Int’l Electron Devices Meeting, pp.1-8, Dec. 2006
[2] Fettweis, “Wave digital filters: Theory and practice,” Proceedings of the IEEE, vol. 74, no. 2, pp. 270–327, 1986.
[3] K. Meerkotter and R. Scholz, “Digital simulation of nonlinear circuits by wave digital filter principles,” IEEE Int’l Symp. on Circuits and Systems, pp. 720–723, 1989.
[4] H. Kutuk and S.-M. Kang, “A field-programmable analog array (FPAA) using switched-capacitor techniques,” in Proc. IEEE Int’l Symp. on Circuits and Systems, vol. 4, 1996, pp. 41-44, 1996.
[5] E. K. Lee and W. L. Hui, “A novel switched-capacitor based field-programmable analog array architecture,” in Field-Programmable Analog Arrays, Springer, pp. 33-50, 1998.
[6] E. K. Lee and P. G. Gulak, “A transconductor-based field-programmable analog array,” in Proc. IEEE Int’l Solid-State Circuits Conf., pp. 198-199, 1995.
[7] B. Pankiewicz, M. Wojcikowski, S. Szczepanski, and Y. Sun, “A field programmable analog array for CMOS continuous-time OTA-C filter applications,” IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 125-136, 2002.
[8] T. S. Hall, C. M. Twigg, J. D. Gray, P. Hasler, and D. V. Anderson, “Large-scale field-programmable analog arrays for analog signal processing,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 52, no. 11, pp. 2298-2307, 2005.
[9] J. Suh, N. Suda, C. Xu, N. Hakim, Y. Cao, B. Bakkaloglu, “Programmable ANalog Device Array (PANDA): A methodology for transistor-Level analog emulation,” IEEE Trans. on Circuits and Systems I: Regular Papers , vol. 60, no. 6, pp. 1369-1380, Jun. 2013.
[10] R. Zheng, J. Suh, C. Xu, N. Hakim, B. Bakkaloglu, and Y. Cao, “Programmable analog device array (PANDA): a platform for transistor-level analog reconfigurability,” in Proc. IEEE Design Automation Conf., pp. 322-327, 2011.
[11] N. Kapre, A. DeHon, “SPICE2: Spatial processors interconnected for concurrent execution for accelerating the SPICE circuit simulator using an FPGA,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 1, pp. 9-22, Jan. 2012.
[12] A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing, 3rd ed. Upper Saddle River, NJ, USA: Prentice Hall Press, 2009.
[13] J. G. Proakis and D. K. Manolakis, Digital Signal Processing – Principles, Algorithms, and Applications, 4rd ed. New Jersey, USA: Pearson Prentice Press, 2007.
[14] K. Neerkotter and R. Scholz, “Digital simulation of nonlinear circuits by wave digital filter principles,” in Proc. IEEE Int. Symp. Circuits and System, vol.1, May 1989, pp. 720-723.
[15] G. De Sanctis and A. Sarti, “Virtual analog modeling in the wave-digital domain,” IEEE Trans. on Audio, Speech, and Language Processing, vol. 18, no. 4, pp. 715-727, May 2010.
[16] A. Sarti and G. D. Poli, “Toward Nonlinear Wave Digital Filters,” IEEE Trans. on Signal Processing, vol. 47, no. 6, pp. 1654-1668, 1999.
[17] S. Petrausch and R. Rabenstein, “Wave digital filters with multiple nonlinearities,” in Proc. European Signal Processing Conference, 2004.
[18] B. J. Sheu, D. L. Scharfetter, P.-K. Ko, and M.-C. Jeng, “Bsim: Berkeley short-Channel IGFET model for MOS transistors,” IEEE J. Solid-State Circuits, vol. 22, no. 4, pp. 558–566, 1987.
[19] T. Shima, T. Sugawara, S. Moriyama, and H. Yamada, “Three-dimensional table look-up MOSFET model for precise circuit simulation,” IEEE J. Solid-State Circuits, vol. 17, no. 3, pp. 449-454, 1982.
[20] S.A Dyer, J.S Dyer, “Cubic-spline interpolation. 1” IEEE Instrumentation & Measurement Magazine, vol. 4, no. 1, pp. 44-46
[21] S. Khotpanya, S. Kittiratsatcha, I. Kazuhisa, “A magnetic model of a three-phase switched-reluctance machine using cubic spline interpolation technique” Power Electronics and Drives Systems, vol. 2, pp. 1167-1170
[22] T. Schwerdtfeger and A. Kummert, “A Multidimensional signal processing Approach to Wave Digital ‘Filters With Topology-Related Delay-Free Loops”, in Proc. IEEE Int’l Conf. on Acoustic, Speech and Signal Processing, 2014.

指導教授

周景揚(Jing-Yang Chou)

審核日期

2015-8-17

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