應用四階共振腔之互補式金氧半導體四相位雙頻振盪器暨使用轉導提升之5 GHz壓控振盪器整合除頻器與X-band 鎖相迴路之研製

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：115

、訪客IP：3.16.51.137

姓名

曾紹齊(Shao-Chi Tseng) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用四階共振腔之互補式金氧半導體四相位雙頻振盪器暨使用轉導提升之5 GHz壓控振盪器整合除頻器與X-band 鎖相迴路之研製
(Implementations on Dual-band CMOS Quadrature Voltage Controlled Oscillator Using 4th Order Resonator, 5 GHz Gm-boosted VCO with Integrated Frequency Divider and X-band Quadrature Phase Locked Loop)

相關論文

★ 應用於筆記型電腦數位電視單極天線之研製	★ 應用於數位機上盒與纜線數據機之電纜多媒體傳輸標準多工濾波器
★ 印刷共面波導饋入式多頻帶與超寬頻天線設計	★ 微波存取全球互通頻段前向匯入式功率放大器與高效率Class F類功率放大器暨壓控振盪器電路之研製
★ 應用於矽基功率放大器與混頻器之傳輸線型變壓器研究	★ 應用於V-頻段射頻收發機前端電路之低功耗源極注入式混頻器之研製
★ 應用積體電路上方後製程與整合被動元件於互補式金氧半導體製程之系統封裝研究	★ 應用fT-倍頻電路架構於毫米波壓控振盪器與注入鎖定除頻器之研製
★ 應用傳輸線型變壓器於X/K–Ka/V頻段全積體整合之寬頻互補式金氧半導體功率放大器研製	★ 應用於K / V 頻段低功耗混頻器之研製
★ 應用於K/V頻段之低功耗CMOS低雜訊放大器之研究	★ 應用於5-GHz CMOS射頻前端電路之低電壓自偏壓式混頻器與高線性化功率放大器之研製
★ 應用於 K 頻段射頻接收機之寬頻低功耗 CMOS 低雜訊放大器之研製	★ 應用磁耦合變壓器於K頻段之低功耗互補式金氧半導體壓控振盪器研製
★ 應用於K頻段之單向化全積體整合功率放大器與應用於V頻段之寬頻功率放大器研製	★ 應用於C/X頻段全積體整合之互補式金氧半導體寬頻低功耗降頻器與寬頻功率混頻器之研製

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 ( 永不開放)

摘要(中)

本論文使用tsmcTM 0.18-um製程來實現收發機中本地振盪源的相關電路；本論文首先將介紹雙頻壓控振盪器的操作機制，再來討論四相位振盪器的產生機制，並設計使用轉導提升之壓控振盪器整合除頻器，最後實現一個具有四相位輸出的鎖相迴路，實作電路的量測結果會用來驗證電路的設計理論。本文內容包含三個電路，內容如下所述：
一、應用四階共振腔與直接注入耦合之雙頻四相位壓控振盪器之研製
本電路利用四階共振腔來切換兩個振盪頻率，使用直接注入耦合來產生四相位的輸出並且使功耗得以減少，低頻段的調頻範圍可以從2.45 ~ 2.7 GHz，高頻段的調頻範圍可以從4.8 ~ 5.2 GHz，低頻段與高頻段的相位雜訊在偏移1 MHz處分別為-116 dBc/Hz與-109 dBc/Hz，電路功耗分別為3.8 mW與5.04 mW，電路的優化指數（FoM）分別為-178 dBc/Hz與-176 dBc/Hz，晶片面積為0.98 × 0.97 mm2。
二、使用轉導提升與電流再利用之壓控振盪器整合除頻器之研製
本電路包含一顆壓控振盪器與電流模式邏輯除頻器(CML Divider)，壓控振盪器的部分使用轉導提升的技術來加大擺幅並降低相位雜訊，壓控振盪器的可調頻率範圍為5.4 ~ 6.2 GHz，除頻器的除頻範圍為2.7 ~ 3.1 GHz，壓控振盪器與除頻器的相位雜訊分別為-116 dBc/Hz與-122.3 dBc/Hz，電路功耗為3.84 與5.3 mW，晶片面積為0.64 × 0.9 mm2。
三、X-band四相位鎖相迴路之研製
本電路包含使用轉導提升技術的四相位壓控振盪器，電流模式邏輯除頻器，單一時脈除頻器(TSPC Divider)，相位頻率檢測器(PFD)、充電汞(CP)、迴路濾波器(Loop Filter)，四相位壓控振盪器採用轉導提升的技術來降低相位雜訊，參考頻率為42MHz，操作頻率在10.75 GHz，整體功耗為54mW，晶片面積為0.92 × 1.03 mm2。

摘要(英)

The mobile wireless has been developed rapidly in recent years. The demands of faster internet also increase dramatically. Therefore, the high performance RF transceivers are needed. The design goals of the recent RF transceivers are like high data rate, low power consumption and small size. Such as Multi-mode and broadband are used to achieve those target. The local oscillator is a key component in RF transceivers. It usually realized by voltage controlled oscillator (QVCO) or phase locked loop (PLL). This thesis includes a dual-band quadrature voltage controlled oscillator (QVCO), a VCO integrated with divider and a quadrature phase locked loop. All circuits are fabricated in tsmcTM 0.18-m CMOS technology.
Chapter 1 is the motivation of the research system standards. And chapter 2 introduces QVCO and presents a dual-band QVCO. The dual-band operation is realized by 4th order resonant without using switches. Direct-Injection coupled technique can reduce power consumption. This design is fabricated in 0.18-μm CMOS technology. The measured low band frequency tuning range is from 2.45 GHz to 2.7 GHz. The high band frequency tuning range is from 4.8 GHz to 5.2 GHz. The phase noise of low band and high band are -116 dBc/Hz and -109 dBc/Hz respectively at 1-MHz offset. The power consumption of low band and high band are 3.8 mW and 5.04 mW respectively. The FoM of low band and high band are -178 dBc/Hz and -176 dBc/Hz respectively. The chip area is 0.98 × 0.97 mm2.
Chapter 3 presents a VCO integrated with a frequency divider. Gm-boosted and current-reused technique are used in VCO design. The frequency divider topology is current mode logic divider(CML). The VCO has improved phase noise performance by using gm-boosted technique. This design is fabricated in 0.18-μm CMOS technology. The measured VCO frequency tuning range is from 5.4 GHz to 6.2 GHz. The divider frequency range is from 2.7 GHz to 3.1 GHz. The phase noise of VCO and divider are -116 dBc/Hz and -122.3 dBc/Hz respectively at 1-MHz offset. The power consumption of VCO and divider are 3.8 mW and 5.3 mW respectively. The chip area is 0.64 × 0.9 mm2.
Chapter 4 introduces phase-locked loop and present a quadrature phase locked loop. This design includes a QVCO, CML divider, TSPC divider, phase and frequency detector, charge pump and low pass filter. The QVCO utilizes gm-boosted technique to have better phase noise performance. The reference frequency is 42 MHz. The output frequency is 10.75 GHz. The total power consumption is 54 mW. The chip area is 0.92 × 1.03 mm2.
Chapter 5 is about conclusion and future works.

關鍵字(中)

★ 四階共振腔
★ 雙頻振盪器
★ 四相位
★ 鎖相迴路

關鍵字(英)

論文目次

摘要 I
Abstract II
誌謝 IV
目錄 VI
圖目錄 VIII
表目錄 X
第一章緒論 1
1-1 研究動機 1
1-2 研究成果 2
1-3 章節介紹 2
第二章應用四階共振腔與直接注入耦合之雙頻四相位壓控振盪器 3
2-1 四相位壓控振盪器簡介 3
2-2 電路架構與分析 3
2-2-1 四階共振腔切換技術簡介 3
2-2-2 直接注入耦合技術簡介 6
2-2-3 應用四階共振腔與直接注入耦合之雙頻四相位壓控振盪器 9
2-2-4 量測與模擬結果 12
2-2-5 結果比較與討論 21
第三章使用轉導提升與電流再利用之壓控振盪器整合除頻器 24
3-1 電路架構與分析 24
3-1-1 轉導提升技術簡介 24
3-1-2 電使用轉導提升與電流再利用之壓控振盪器 28
3-1-3 電流模式邏輯除頻器 31
3-1-4 使用轉導提升與電流再利用之壓控振盪器整合除頻器 33
3-1-5 量測與模擬結果 34
3-1-6 結果比較與討論 42
第四章 X-band四相位鎖相迴路 44
4-1 鎖相迴路介紹 44
4-2 電路架構與分析 47
4-2-1 X-band四相位鎖相迴路 47
4-2-2 四相位壓控振盪器設計 48
4-2-3 電流模式邏輯除頻器 50
4-2-4 真單一相位時脈除頻器 52
4-2-5 相位頻率檢測器 52
4-2-6 充電汞 53
4-2-7 迴路濾波器 55
4-2-8 模擬結果 59
4-2-9 結果比較與討論 62
第五章結論 64
5-1 結論 64
5-2 未來方向 65
參考文獻 66

參考文獻

[1] C.-H. Lin and H.-Y. Chang, “A low-phase-noise CMOS quadrature voltage-controlled oscillator with self-injection-coupled technique,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 10, pp. 623–627,
[2] S. L. Jang, C. C. Shih, C. C. Liu, C. W. Chang, and C. W. Hsue, “CMOS quadrature VCOs using the varactor coupling technique,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 9, pp. 498–500, Sep. 2011.123
[3] H.-Y. Chang and Y.-T. Chiu, “K-band CMOS differential and quadrature voltage-controlled oscillators for low phase-noise and low-power applications,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 1, pp. 46–59, Jan. 2012
[4] H.-J. Chang, C. Lee, and T.-Y. Yun, “CMOS QVCO with current-reuse, bottom-series coupling, forward body biasing techniques,” IEEE Microw. Wireless Compon. Lett., vol. 24, no. 9, pp. 608–610, Sep. 2014.
[5] J. Kim, J. Shin, S. Kim, and H. Shin, “A wide-band CMOS LC VCO with linearized coarse tuning characteristic,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, pp. 399–403, May 2008.
[6] Sheng-Lyang Jang, Yuan-Kai Wu, Cheng-Chen Liu, and Jhin-Fang Huang, “A Dual-Band CMOS Voltage-Controlled Oscillator Implemented With Dual-Resonance LC Tank,” IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 19, NO. 12, DECEMBER 2009.
[7] S. Y. Lee, L. H. Wang, and Y. H. Lin, “A CMOS Quadrature VCO with subharmonic and injection-locked techniques,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 11, pp. 843–847, Nov. 2010.
[8] A. Hajimiri and T. Lee, “Design Issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 717–724, May 1999.
[9] Szu-Ling Liu, Kuan-Han Chen, and Albert Chin, “A Dual-Resonant Mode 10/22-GHz VCO With a Novel Inductive Switching Approach,” IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 7, JULY 2012.
[10] Xinrong Hu, Fengyi Huang , Tao Li, Xusheng Tang, “A Dual-Band LC VCO Using a Switched Current Source for IMT-Advanced and UWB Applications,” Proceedings of International Symposium on Signals, Systems and Electronics (ISSSE2010).
[11] H. L. Kao, D. Y. Yang, A. Chin, and S. P. McAlister, “A 2.4/5 GHz dual-band VCO using a variable inductor and switched resonator,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp. 1533–1536.
[12] Y.-C. Lo and J. Silva-Martinez, “A 5-GHz CMOS LC quadrature VCO with dynamic current-clipping coupling to improve phase noise and phase accuracy,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 7, pp. 2632–2640, Jul. 2013.
[13] S. Saberi and J. Paramesh, “A 11.5–22 GHz dual-resonance transformer-coupled quadrature VCO,” in Proc. IEEE RFIC, 2011, pp. 1–4.
[14] Muh-Dey Wei , Sheng-Fuh Chang , Ye Zhang y Yung-Jhih Yang z, and Renato Negra, “2.4 GHz / 3.5 GHz Dual-Band Wide-Tuning-Range Quadrature VCO using Harmonic-Injection Coupling Technique,” Silicon Monolithic Integrated Circuits in Rf Systems (SiRF), 2014 IEEE 14th Topical Meeting on.
[15] Sheng-Lyang Jang ; Heng-Fa Teng ; Chia-Wei Chang ; Chao-Wei Hsieh, “Quadrature VCO using the composite right-/left-handed dual-resonance resonator,” IEEE CONFERENCE PUBLICATIONS Proceedings of APMC 2012, Kaohsiung, Taiwan, Dec. 4-7, 2012.
[16] Pei-Kang Tsai1, Tzuen-Hsi Huang1, Yu-Ting Chen2, “Dual-band quadrature voltage-controlled oscillator using differential inner-diamond-structure switchable inductor,” Circuits, Devices & Systems, IET (Volume:7 , Issue: 6 ) November 2013.
[17] S.-L. Liu, K.-H. Chen, and A. Chin, “A dual-resonant mode 10/22-GHz VCO with a novel inductive switching approach,” IEEE Trans. Microw. Theory Tech., vol. 60, pp. 2165–2177, Jul. 2012.S.-L. Jang, S. Jain, “Dual C- and S-Band CMOS VCO Using the Shunt Varactor Switch, ” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, pp.1,1
[18] S. Rong and H. C. Luong, “Analysis and design of transformer-based dual-band VCO for software-defined radios,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 3, pp. 449–462, Mar. 2012.
[19] S.-L. Jang, S. Jain, “Dual C- and S-Band CMOS VCO Using the Shunt Varactor Switch, ” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, pp.1,1
[20] C. Yang et al., “A 20/40-GHz dual-band voltage-controlled frequency source in 0.13um CMOS,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 8, pp. 2008–2016, Oct. 2011.
[21] J. H. Tsai, C. Y. Hsu, C. H. Chao, “An X-band 9.75/10.6 GHz low-power phase-locked loop using 0.18-um CMOS technology,” Microwave Integrated Circuits Conference (EuMIC), pp.238-241, 2015.
[22] J.F. Huang, C.C. Mao and R.Y. Liu, The 10 GHz wide tuning and low phase-noise PLL chip design, IEEE int. Secruity and Identification conf., 2011, pp.157-160.
[23] J.-H. Tsai, C.a-H. Chao, and H.-D. Shih, “A X-band fully integrated CMOS frequency synthesizer,” in Proc. Asia-Pacific Microwave Conf., Dec. 2012, pp. 1226-1228.
[24] C.-T. Lu, H.-H. Hsieh, and L.-H. Lu, “A low-power quadrature VCO and its application to a 0.6-V 2.4-GHz PLL,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 4, pp. 793–802, Apr. 2010.
[25] 劉深淵，楊清淵，鎖相迴路，滄海書局，民國一百年。

指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2016-8-23

推文