博碩士論文 103521108 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:111 、訪客IP:18.191.192.81
姓名 吳治成(Zhi-Cheng Wu)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 具高導通電流常關型銻砷化鎵/砷化銦鎵異質接面穿隧式場效電晶體之研究
(Bandgap Engineering for Normally-off GaAsSb/InGaAs Hetero-junction Tunneling Field-Effect Transistors with High On-state Current)
相關論文
★ 磷化銦異質接面雙極性電晶體元件製作與特性分析★ 氮化鎵藍紫光雷射二極體之製作與特性分析
★ 氮化銦鎵發光二極體之研製★ 氮化銦鎵藍紫光發光二極體的載子傳輸行為之研究
★ 次微米磷化銦/砷化銦鎵異質接面雙極性電晶體自我對準基極平台開發★ 以 I-Line 光學微影法製作次微米氮化鎵高電子遷移率電晶體之研究
★ 矽基氮化鎵高電子遷移率電晶體 通道層與緩衝層之成長與材料特性分析★ 磊晶成長氮化鎵高電子遷移率電晶體 結構 於矽基板過程晶圓翹曲之研析
★ 氮化鎵/氮化銦鎵多層量子井藍光二極體之研製及其光電特性之研究★ 砷化銦量子點異質結構與雷射
★ 氮化鋁鎵銦藍紫光雷射二極體研製與特性分析★ p型披覆層對量子井藍色發光二極體發光機制之影響
★ 磷化銦鎵/砷化鎵異質接面雙極性電晶體鈍化層穩定性與高頻特性之研究★ 氮化鋁中間層對氮化鋁鎵/氮化鎵異質接面場效電晶體之影響
★ 不同濃度矽摻雜之氮化鋁銦鎵位障層對紫外光發光二極體發光機制之影響★ 二元與四元位障層應用於氮化銦鎵綠光二極體之光性分析
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 金氧半場效電晶體(MOSFET)是以漂移-擴散的機制來傳導電流,受限於此機制,其開關時閘極需要至少60 mV來改變十倍的通道電流,也就是其次臨限擺幅(Subthreshold Swing)最理想狀況下僅能降至60 mV/decade。在考慮低功率損耗時,具有陡峭開關特性的穿隧式場效電晶體(TFETs)被認為有應用在新世代CMOS元件的潛力。目前,國內外已經有許多的矽/鍺材料穿隧式場效電晶體研究成果,優點是容易與傳統矽材料/元件整合且製程成熟度高,但缺點是材料能隙大且能帶組合受限,導致穿隧電流偏低或漏電流太大,因此以能隙較小的三五族材料搭配異質結構能帶工程,或可解決上述問題,成為未來穿隧式場效電晶體的選擇。本論文即以三五族異質接面穿隧場效電晶體為研究對象,利用模擬方式研究如何設計常關型、高電流、低次臨限擺幅的穿隧場效電晶體結構。研究內容包括建立三五族穿隧場效電晶體物理模型,以具第二型異質接面的銻砷化鎵/砷化銦鎵(GaAsSb/InGaAs)結構為主,模擬元件磊晶結構、閘極氧化層位置、材料缺陷和摻雜濃度等參數對元件直流特性之影響。模擬結果顯示,吾人可改變銻砷化鎵/砷化銦鎵結構之成分組合而降低穿隧的等效位能障,以有效提高導通電流,但也同時會提高關閉時之漏電流,此一致命的缺點將使穿隧式電晶體無法運用在節能電路之中。因此,吾人以能帶工程的方式,將GaAs0.51Sb0.49/In0.53Ga0.47As源極-通道接面之間加入一層砷化銦(InAs)量子井,將源極-通道接面的等效位障由0.5 eV降至0.1 eV,藉此將導通電流提高至89 μA/μm,同時將漏電流維持在5×10-8 μA/μm,此接面能帶的調整對於元件特性有相當顯著地提升。為了持續優化直流特性,吾人提出以具組成梯度(Graded)的砷化銦鎵量子井來取代上述之砷化銦量子井,使元件同時具有高導通電流與低漏電流的特性,並且具有高於50 mV的臨限電壓以降低閘極雜訊之影響,完成高導通電流常關型穿隧式場效電晶體之設計。
摘要(英) Since the channel current of MOSFETs is governed by the drift-diffusion mechanism, their subthreshold swing is limited to 60 mV/decade or higher at room temperature. Whereas, tunnel field-effect transistors (TFETs), whose current conduction is based on quantum mechanical band-to-band tunneling mechanism that gives a sub-60 mV/decade subthreshold slope, have been considered a promising energy-efficient device for low voltage and low power circuits. Since the inception of this proposal, TFETs based on Si/Ge material system have been demonstrated by a few groups. However, the devices are limited by either a low on-current or a high off-current due to the unfavored bandgap and band alignment of Si/Ge. Attention is then switched to narrow bandgap III-V compounds as the aforementioned issues could be solved by band gap engineering. This study is focused on III-V TFETs, aiming at the design and analysis of a normally-off TFET with high-on current. It covers the setup of a physical model in the TCAD tool, the effects of band alignments, gate position, and doping concentration on the electrical properties of the type-II band lineup GaAsxSb1-x/InyGa1-yAs heterojunction TFETs. Our simulation indicate that although GaAsxSb1-x/InyGa1-yAs TFETs could be designed to have a small Ebeff at the hetero-interface for high-on current, their high off-state current manifest themselves unacceptable for practical use. To solve this issue, a GaAs0.51Sb0.49/InAs/In0.53Ga0.47As TFET with an InAs quantum well (QW) is proposed to reduce the Ebeff from 0.5 eV to 0.1 eV at the source/channel interface, leading to an on-state current increasing from 27 A/m to 89 A/m at VGS=VDS=0.5 V, while the IOFF still maintains on the order of 10-7 μA/μm at VGS=0 V, simultaneously. To improve the device performance further and increase noise immunity at the gate, a graded InGaAs QW is designed to replace the InAs QW in the GaAs0.51Sb0.49/In0.53Ga0.47As TFET above. On this design, a normally-off TFET with high on-state current and threshold voltage greater than 50 mV has been achieved.
關鍵字(中) ★ 銻砷化鎵/砷化銦鎵
★ 穿隧式場效電晶體
關鍵字(英) ★ GaAsSb/InGaAs
★ Tunneling Field-Effect Transistors
論文目次 摘要 I
Abstract III
誌謝 IV
目錄 V
圖目錄 VIII
表目錄 XII
第一章 導論 1
1.1 背景與相關研究 1
1.2 研究動機 13
1.3 論文架構 14
第二章 穿隧式場效電晶體原理及穿隧模型 15
2.1 前言 15
2.2 穿隧理論與穿隧電流 16
2.3 穿隧模型 20
2.4 模擬穿隧式場效電晶體的重要參數 23
2.5 結論 25
第三章 銻砷化鎵/砷化銦鎵異質接面穿隧式場效電晶體之電特性的模擬與探討 26
3.1 前言 26
3.2 銻砷化鎵/砷化銦鎵異質結構設計 27
3.3 摻雜濃度改變後的特性模擬與探討 32
3.3.1 源極濃度變異後電性的模擬與探討 33
3.3.2 汲極濃度變異後電性的模擬與探討 35
3.3.3 源極濃度和汲極濃度電性最佳化的模擬與探討 37
3.4 閘極氧化層接面對齊與界面缺陷的模擬與探討 39
3.4.1 閘極氧化層接面對齊電性的模擬與探討 39
3.4.2 界面缺陷電性的模擬與探討 43
3.5 結論 45
第四章 銻砷化鎵/砷化銦鎵穿隧式場效電晶體異質接面能帶工程優化之模擬與探討 47
4.1 前言 47
4.2 銻砷化鎵/砷化銦鎵等效位障(Ebeff)變異後電性的模擬與探討 48
4.3 具插入層之銻砷化鎵/砷化銦鎵電性的模擬與探討 53
4.3.1 不同插入層厚度之模擬與探討 53
4.3.2 插入層成分變異之模擬與探討 55
4.4 具插入層之銻砷化鎵/砷化銦鎵電性最佳化的模擬與探討 57
4.5 結論 60
第五章 總結 62
參考文獻 63
附錄 66
參考文獻 [1] I.R. Committee, “International Technology Roadmap for Semiconductors,” 2011 Edition. Semiconductor Industry Association.
[2] H. Iwai, “Future of Logic Nano CMOS Technology,” IEEE EDS DL, IIT-Bombay, Jan. 14, 2015.
[3] J. Appenzeller, Y.-M. Lin, J. Knoch and Ph. Avouris, “Band-to-Band Tunneling in Carbon Nanotube Field-Effect Transistors,” The American Physical Society, Nov. 2004
[4] S. Mokerjea, D. Mohata, R. Krishnan, J. Singh, A. Vallet, A. Ali,
T. Mayer, V. Narayanan, D. Schlom, A. Liu and S. Datta, “Experimental Demonstration of 100nm Channel Length In0.53Ga0.47As-based Vertical Inter-band Tunnel Field Effect Transistors (TFETs) for Ultra Low-Power Logic and SRAM Applications,” IEEE International Electron Devices Meeting (IEDM), 2009, pp. 13.7.1-13.7.3
[5] D. K. Mohata, R. Bijesh, S. Mujumdar, C. Eaton, R. Engel-Herbert,
T. Mayer, V. Narayanan, J. M. Fastenau, D. Loubychev, A. K. Liu and
S. Datta, “Demonstration of MOSFET-Like On-Current Performance in Arsenide/Antimonide Tunnel FETs with Staggered Hetero-junctions for 300mV Logic Applications,” IEEE International Electron Devices Meeting (IEDM), 2011, pp. 33.5.1-33.5.4
[6] R. Bijesh, H. Liu, H. Madan, D. Mohata, W. Li, N. V. Nguyen,
D. Gundlach, C. A. Richter, J. Maier, K. Wang, T. Clarke, J. M. Fastenau, D. Loubychev, W. K. Liu, V. Narayanan and S. Datta, “Demonstration of In0.9Ga0.1As/GaAs0.18Sb0.82 Near Broken-gap Tunnel FET with ION=740 uA/um, GM=700 uS/um and Gigahertz Switching Performance at VDS=0.5V,” IEEE International Electron Devices Meeting (IEDM), 2013, pp. 28.2.1-28.2.4
[7] G. Dewey, B. Chu-Kung, J. M. Fastenau,J. Kavalieros, R. Kotlyer,
W. K. Liu, D. Lubyshev, M. Metz, N. Mukherjee, P. Oakey,
R. Pillarisetty, M. Radosavljevic, H. W. Then and R. Chu, “Fabrication, Characterization, and Physics of III-V Heterojunction Tunneling Field Effect Transistors (H-TFET) for Steep Sub-Threshold Swing,” IEEE International Electron Devices Meeting (IEDM), 2011, pp. 33.6.1-33.6.4
[8] X. Zhao, A. Vardi and Jesús A. del Alamo, “InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs Fabricated by a Top-down Approach,” IEEE International Electron Devices Meeting (IEDM), 2014, pp. 25.5.1-25.5.4
[9] D. K. Mohata, R. Bijesh, Y. Zhu, M. K. Hudait, R. Southwick, Z. Chbili, D. Gundlach, J. Suehle, J. M. Fastenau, D. Loubychev, A. K. Liu,
T. S. Mayer, V. Narayanan and S. Datta, “Demonstration of Improved Heteroepitaxy, Scaled Gate Stack and Reduced Interface States Enabling Heterojunction Tunnel FETs with High Drive Current and High On-Off Ratio,” IEEE VLSI Technology (VLSIT), 2012, pp. 53-54.
[10] B. Rajamohanan, Rahul Pandey, Varistha Chobpattana, Canute Vaz, David Gundlach, Kin P. Cheung, John Suehle, Susanne Stemmer and Suman Datta, “0.5 V Supply Voltage Operation of In0.65Ga0.35As/GaAs0.4Sb0.6 Tunnel FET,” IEEE Electron Device Lett., vol. 36, 2015, pp. 20-22
[11] A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, vol. 479, Nov 17, 2011,
pp. 329-37
[12] A. Seabaugh, “The Tunneling Transistor,” IEEE Spectrum, Oct. 2013, pp. 35-38
[13] S. M. Sze and K.K. Ng, “Physics of Semiconductor Devices. (3rd ed.) Canada: John Wiley & Sons, Inc., 2007, ch.8.
[14] “Sentaurus Device User Guide Version D-2010.03,” March 2010.
[15] L. D. Michielis, M. Iellina, P. Palestri, A. M. Ionescu and L. Selmi, “Tunneling Path Impact on Semi-Classical Numerical Simulations of TFET Devices,” 12th International Confernece on Ultimate Integration on Silicon, 2011, pp. 1-4.
[16] A. R. Trivedi, R. Pandey, H. Liu, S. Datta and S. Mukhopadhyay, “Gate/Source Overlapped Heterojunction Tunnel FET for non-Boolean Associative Processing with Plasticity,” IEEE International Electron Devices Meeting (IEDM), 2014, pp. 17.8.1-17.8.4
指導教授 綦振瀛(Jen-Inn Chyi) 審核日期 2016-8-26
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明