三維集成電路的發展與挑戰

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姓名

李牧民(Mu-Ming Lee) 查詢紙本館藏

畢業系所

機械工程學系

論文名稱

三維集成電路的發展與挑戰
(The Development and Challenges of 3D IC)

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摘要(中)

本論文呈現的是一個針對三維集成，包含三維集成封裝、
三維集成電路，以及使用矽穿孔技術的三維集成電路之深入探
討研究報告。三維集成、封裝、三維集成電路以及矽穿孔等將
在本研究中被定義，二維集成電路到三維集成電路的演化過程
將被詳細說明，而整個三維集成電路和矽穿孔技術的架構和
製程過程也都將在此論文中詳細呈現。本論文也將針對三維集
成電路最重要核心結構的中介層做出詳細定義，也將針對中介
層的完整製程流程做說明。最後，三維集成電路之檢測機制，
應用範圍以及三維集成電路所將面臨之挑戰也被討論。

摘要(英)

This thesis presents a survey of 3D integration, including 3D IC packing, 3D IC integration and also a survey of 3D Integrated Circuits using Through Silicon Vias (TSV). 3D integration, packing, 3D IC Integrated Circuits and also TSV will be defined, the evolution of 2D IC’s to 3D IC’s and the rationale for moving to these systems will be given, and a whole overview of the construction and process of the 3D Integrated Circuit and TSV will be presented. This thesis also will give a detail caption about the interposer, which is the heart of 3D IC, and also the manufacturing process of the interposer. Lastly, the testing mechanism, application and challenges of 3D Integrated Circuits using TSVs will be discussed.

關鍵字(中)

★ 三維集成
★ 三維集成封裝
★ 三維集成電路
★ 矽穿孔
★ 中介層

關鍵字(英)

★ 3D integration
★ 3D IC packing
★ 3D IC
★ Through Silicon Via
★ TSV
★ Interposer

論文目次

摘要 iv
Abstract v
誌謝 vi
目錄 vii
圖目錄 xi
第一章：緒論 1
1-1前言 1
1-2 研究動機與目的 2
1-3 研究架構 5
第二章：資料蒐集方法 7
2-1 網路搜尋引擎 7
2-1-1 台灣碩博士論文知識加值系統(NDLTD) 7
2-1-2 Google專利搜尋引擎(Google Patent) 8
2-1-3 Google學術搜尋引擎(Google Scholar) 8
2-1-4 HyRead Journal台灣全文資料庫 9
2-1-5 Web of Science 10
2-1-6 IEEE Xplore Digital Library 10
2-1-7 Science Direct On Line (SDOL) 11
2-1-8 CNKI 中國知識網絡服務平台 12
2-2 其他參考網站 13
2-2-1 美國專利商標局 (United States Patent and Trademark Office, USPTO) 官網 13
2-2-2 工業技術研究院 (Industrial Technology Research Institute, ITRI) 14
2-2-3 EET電子工程專輯 15
2-2-4 MoneyDJ 財經知識庫 15
2-2-5 Materialsnet 材料世界網 16
2-2-6 NAiP 北美智權股份有限公司官網 17
2-2-7 新電子科技雜誌 Micro-Electronics Magazine 18
2-2-8 休斯微技術股份有限公司(SUSS MicroTec)官網 19
第三章：結果與討論 21
3-1 三維集成的起源與發展經過 21
3-1-1 三維矽集成 22
3-1-2 三維芯片集成 23
3-2 三維集成電路的建構 25
3-2-1 三維集成電路中介層的製程流程 26
3-2-1-1 導孔的形成 27
3-2-1-2 氧化/邊界/晶種層的沉積 30
3-2-1-3 導電體的填充/電鍍 32
3-2-1-4 化學機械研磨 37
3-2-1-5 前端金屬化製程 38
3-2-1-6 承載/暫時性晶圓接合 38
3-2-1-7 晶圓薄化 39
3-2-1-8 後端金屬化製程 40
3-2-1-9 凸塊製程 40
3-2-1-10 去接合 41
3-2-2晶圓/芯片接合技術 41
3-2-2-1 晶圓對位製程 43
3-2-2-2 晶圓/芯片接合製程(接合方法) 45
3-2-2-3 晶圓接合方向 48
3-2-2-4 晶圓/芯片接合型式 49
3-2-3 三維集成電路的整合與封裝 50
3-2-3-1 系統單芯片 51
3-2-3-2 系統級封裝 52
3-2-3-3 系統單芯片和系統級封裝之細部比較與分析 53
3-2-3-4 系統整合封裝 54
3-2-3-5 芯片堆疊封裝 54
3-3 2D, 2.5D與3D 集成電路的分析與比較 55
3-4 3D IC的檢測機制 60
3-4-1 晶圓檢測 60
3-4-2 芯片檢測 62
3-5 3D IC的市場應用 64
3-5-1 3D IC記憶體應用 64
3-5-2 3D IC影像感測器應用 65
3-6 3D IC與垂直整合的優勢 66
3-7 3D IC將面臨之未來挑戰 69
第四章：結論與未來展望 73
4-1 結論 73
4-2 未來展望 76
參考文獻 78

參考文獻

[1] Gordon Moore, “Cramming More Components Onto Integrated Circuits”, Electronics, Vol. 38, No. 8, April 19, 1965.
[2] Lau, J. H., Reliability of RoHS Compliant 2D & 3D IC Interconnects, McGraw-Hill, NY, 2011.
[3] Robert Minvielle and Magdy Bayoumi,“ On Through Silicon Vias as used in Three Dimensional Integrated Circuits”, 2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC),IEEE, 2013.
[4] Stuby, K.; Falls, W., Hourglass-shaped Conductive Connection Through Semiconductor Structures, United States Patent 3,648,131, Mar. 7, 1972.
[5] Kish, Laszlo B.”End of Moore’s law: thermal (noise) death of integration in micro and nano electronics.” Physics Letters A 305.3 (2002): 144-149.
[6] Schulz, Max.”The end of the road for silicon?.” Nature 399.6738 (1999):729-730.
[7] Baliga, John. ”Chips go vertical [3D IC interconnection].” Spectrum, IEEE 41.3 (2004): 43-47.
[8] Said F. Al-Sarawi et.al, “A review of 3D Packaging Technology” IEEE Transactions on CPMT Part-B, Vol.21, No.1, 1998, pp. 2-14.
[9] Larry Wu et,al, “The Advent of 3D Package Age”, IEEE/CPMT International Electronics Manufacturing Technology Symposium, 2000, pp.102-107.
[10] Lau, J. H., “Heart and Soul of 3D IC Integration”, posted at 3D InCites on June 29,2010.
[11] Lau, J. H., “Who Invented the TSV and When?” posted at 3D InCites on April 24,2010.

[12] Toshiba Corporation,“Toshiba to enhance competitiveness in image sensor business by bringing manufacturing of CMOS camera modules for mobile phones in-house”, 01 October, 2007.
[13] 許明哲，“先進微電子3D-IC構裝, Advanced Microelectronic 3D-IC Packaging”, Sep. 2011.
[14] Lau, J. H., “Reliability of RoHS Compliant 2D & 3D IC Interconnects”, McGraw-Hill, NY,2011.
[15] Akasaka, Y., “Three-dimensional IC Trends”, Proceedings of the IEEE, Vol. 74, No. 12, December 1986, pp. 1703-1714.
[16] Akasaka, Y., and Nishimura, T., “Concept and Basic Technologies for 3-D IC Structure”,IEEE Proceedings of International Electron Devices Meetings, Vo. 32, 1986, pp. 488-491.

[17] Lau, J. H.,“ Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration”, 2011 International Symposium on Advanced Packaging Materials (APM),IEEE.
[18] Kang, U., H. Chung, S. Heo, D. Park, H. Lee, J. Kim, S. Ahn, S. Cha, J. Ahn, D. Kwon, J. Lee, H. Joo, W. Kim, D. Jang, N. Kim, J. Choi, T. Chung, J. Yoo, J. Choi, C. Kim, and Y. Jun, “8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology”, IEEE Journal of Solid-State Circuits, VOL. 45, NO. 1, January 2010, pp.111-119.
[19] Akasaka, Y. ”3D technologies.” Microelectronic Engineering 8.3-4(1988): 219-233.
[20] Takahashi, Shuji, et al. ”Characteristics of thin-film devices for a stack-type MCM.” Multi-Chip Module Conference, 1992. MCMC-92, Proceedings 1992 IEEE. IEEE, 1992.

[21] Takahashi, Kenji, and Masahiro Sekiguchi. ”Through silicon via and 3-D wafer/chip stacking technology.” VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on. IEEE, 2006.
[22] Vempati Srinivasa Rao, Ho Soon Wee, Lee Wen Sheng Vincent, Li Hong Yu, Liao Ebin, Ranganathan Nagarajan, Chai Tai Chong, Xiaowu Zhang, Pinjala Damaruganath, “ TSV Interposer Fabrication for 3D IC Packaging”, 11th Electronics Packaging Technology Conference, 2011,IEEE.
[23] 詹印豐、顏錫鴻、許明哲 / 弘塑科技公司, “TSV製程技術整合分析”,半導體科技, 2015.
[24] 丁敬秀，中芯國際集成電路製造(上海)有限公司，“TSV盲孔的製作方法”，中華人民共和國國家知識財產局，申請公佈號:CN104835776A，2015.08.12.

[25] Yeung Au, Qing Min Wang, Huazhi Li, Jean-Sebastien M. Lehn, Deo V. Shenai, and Roy G. Gordona, “Vapor Deposition of Highly Conformal Copper Seed Layers for Plating Through-Silicon Vias (TSVs)”, Journal of The Electrochemical Society, 159 (6) D382-D385 (2012).
[26] 詹印豐，顏錫鴻，許明哲， “TSV製程技術整合分析”, 半導體科技, 2015.
[27] 張佑祥，陳瑞琴，曾培哲，“3D IC TSV 製程技術簡介”, 工業材料雜誌第345期, 2015.
[28] Tan, Chuan Seng, Ronald J. Gutmann, and L. Rafael Reif. Wafer level 3-D ICs process technology. Springer, 2008.
[29] Tan, Chuan Seng, Ronald J. Gutmann, and L. Rafael Reif. Wafer level 3-D ICs process technology. Springer, 2008.
[30] Lee, PeiIng, John Cronin, and Carter Kaanta. ”Chemical vapor deposition of tungsten (CVD W) as submicron interconnection and via stud.”Journal of The Electrochemical Society 136.7 (1989): 2108-2112.
[31] Ryo Takigawa, Kohei Nitta, Akihiro Ikeda, Mitsuaki
Kumazawa, Toshiharu Hirai, Michio Komatsu, and Tanemasa Asano, “High-speed via hole filling using electrophoresis of Ag nanoparticles”, International 3D Systems Integration Conference, 2015, IEEE
[32] M. Koyanagi, H. Kurino, K. W. Lee, K. Sakuma, N.
Miyakawa, and H.Itani, “Future sytem-on-silicon LSI chips,” IEEE Micro, vol. 18, pp. 17-22, August 1998.
[33] K. Takahashi, H. Terao, Y. Tomita, Y. Yamaji, M. Hoshino, T. Sato, T.Morifuji, M. Sunohara, and M. Bonkohara, “Current status of research and development for three demonsinal chip stacking technology,” Jpn. J.Appl. Phys., vol. 40, pp. 3032-3037, April 2001.
[34] J. Sun, K. Kondo, T. Okamoto, S. Oh, M. Tomisaka, H. Yonemura, and M. Hoshino, “High-Aspect-Ratio Copper Via Filling Used for Three Dimentinal Packaging,” J. Electrochemi. Soc., vol. 150, pp. G355-G358, April 2003.

[35] 張雅嵐，“由3D IC 製程變化看技術發展挑戰”, 半導體智庫，2008.
[36] 張琳一， “志聖壓膜技術再升級展出Temporary Bonding System”, 物聯網 Digitimes, 2012.
[37] 許明哲，“先進微電子3D-IC構裝, Advanced Microelectronic 3D-IC Packaging”, Sep. 2011.
[38] Liu, F., et al. ”A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding.”Electron Devices Meeting, 2008. IEDM 2008. IEEE International.IEEE, 2008.
[39] Kuo, Tzu-Ying, et al. ”Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost.”Electronic Components and Technology Conference, 2008. ECTC 2008.58th. IEEE, 2008.
[40] Tan, Chuan Seng, Ronald J. Gutmann, and L. Rafael Reif. Wafer level 3-D ICs process technology. Springer, 2008.
[41] C.H. Wang et al., “Chip scale studies of BCB based polymer bonding for MEMS packaging”, 2008 Electronic Components and Technology Conference (ECTC), May 27–30, 2008, pp. 1869.
[42] Banqiu Wu, Ajay Kumar, Sesh Ramaswami, “3D IC Stacking Technology”, ISBN 978-0-07-174195-8, 2011, pp 409~435.
[43] Gsele, U., and Q-Y. Tong. ”Semiconductor wafer bonding.” Annual Review of Materials Science 28.1 (1998): 215-241.
[44] L. Di Cioccio, “New Heterostructures & 3-Dimensional Device Obtained at CEA/Leti by the Bonding & Thinning Method,” ECS Trans., vol. 3, no. 6, 2006, pp19
[45] J.Q. Liu, A. Jindal, et all, “Wafer-level assembly of heterogeneous technologies”, The International Conference on Compound Semiconductor Manufacturing Technology, 2003.

[46] C. Christensen, P. Kersten, S. Henke, and S. Bouwstra, “ Wafer through hole interconnects with high vertical wiring densities”, IEEE Trans. Components, Packaging and Manufacturing Technology, A, vol. 19, 1996, p516.
[47] J. Gobet et all, “IC compatible fabrication of through wafer conductive vias”, Proc. SPIE-The International Society for Optical Enginering, vol 3323, 1997.
[48] H. Noh, Kyoung-sik Moon, A. Cannon P. J. Hesketh and C. P. Wang, Proc. IEEE Electron Components and Technology Conference, vol.1, 2004, pp. 924~930.
[49] K. W. Chen, A. W. Topol et all, Pro. IEDM, 2002, pp.943~945.
[50] M. Despont, U. Drechsler, R. Yu, H. B. Pogge and P. Vettiger, Journal of Microelectro-mechanical System, vol. 13, no.6, 2004, pp895~901.

[51] Schmidt, Martin A. ”Wafer-to-wafer bonding for microstructure formation.”Proceedings of the IEEE 86.8 (1998): 1575-1585.
[52] Tan, Chuan Seng, Ronald J. Gutmann, and L. Rafael Reif. “Wafer level 3-D ICs process technology.” Springer, 2008.
[53] C.S. Tan et al., Electrochem. Solid-State Lett. 8 (6) (2005) G147–G149.
[54] Ming-Fang Lai, Shih-Wei Li, Jian-Yu Shih, Kuan-Neng Chen, “Wafer-level three-dimensional integrated circuits (3D IC): Schemes and key technologies”, Microelectronic Engineering 88 (2011) 3282–3286.
[55] 唐經洲，“垂直堆疊優勢多　3D IC倒吃甘蔗”，新通訊元件雜誌 109期，2010年3月。
[56] Clive Maxfield, “2D vs.2.5D vs. 3D ICs”, Designlines Programmable Logic, EE Times, April 2012.
[57] KLA-Tencor Official Website, “http://kla-tencor.com/advanced-packaging/circl-ap.html”.

[58] KLA-Tencor Official Website, “http://kla-tencor.com/advanced-packaging/icos-t830.html”.
[59] 涂志豪， “宜特搶進3D IC檢測”, 中時電子報, 05.2013.
[60] Md S. Hossain, K. I. Masood, A. Barua and S Subrina, “Thermal management of 3-D IC using Carbon Nanotube Thermal Via”, 2012 7th International Conference on Electrical and Computer Engineering, IEEE, December 2012.
[61] 李依頻， “降低TSV成本　濕式蝕刻助攻3D IC”，Micro-Electronics新電子，10.2015.

指導教授

李雄(Shyong Lee)

審核日期

2016-7-1

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