次臨界區運算放大器電路之自動化設計

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林郁芸(Yu-Yun Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

次臨界區運算放大器電路之自動化設計
(Design Automation for Sub-Threshold Operational Amplifier Circuits)

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摘要(中)

現今新興的超低功率消耗的應用，越來越受到大家的關注與重視。為了達到超低功率消耗的需求，以延長產品使用時間，次臨界區(Sub-threshold)電路設計提供了一種解決方法，藉由操作在極低電壓 (Vdd

摘要(英)

Power has become the primary design constraint for chip designers today. To reduce power and increase service time, low-voltage low-power design becomes more and more important. One of the possible ways to achieve this goal is sub-threshold circuit design. By operating transistors at the region that Vdd is less than the transistor threshold voltage (Vdd

關鍵字(中)

★ 次臨界區
★ 兩級式運算放大器
★ 類比設計自動化

關鍵字(英)

★ Sub-threshold
★ Two-stage-OPA
★ Design Automation

論文目次

摘要------------i
Abstract--------ii
致謝------------iii
目錄------------iv
圖目錄----------vi
表目錄----------vii
第一章、緒論-----1
1-1 研究動機-----1
1-2 相關研究-----3
1-2-1 考慮雜訊於電路設計---------3
1-2-2 考慮佈局效應之類比設計自動化工具------4
1-3 問題定義-----5
1-4 論文結構-----6
第二章、背景知識--7
2-1 次臨界區設計--7
2-1-1 次臨界區的設計挑戰-----8
2-1-2 解決方法---9
2-2 電路架構-----12
2-3 電壓驅動設計方法--------14
2-3-1 gm/ID方法--16
2-3-2 限制條件與目標函數----20
2-3-3 取得電晶體尺寸--------22
2-3-4 電壓驅動設計流程------24
第三章、雜訊考量--26
3-1 雜訊型態-----26
3-1-1 射雜訊-----27
3-1-2 閃爍雜訊---28
3-1-3 電路中雜訊的表示-------30
3-2 單級放大器雜訊分析-------31
3-3 兩級式運算放大器雜訊分析--32
3-3-1 第一級雜訊--33
3-3-2 第二級雜訊--36
3-4 目標函數------37
3-4-1 面積目標函數----------37
3-4-2 雜訊目標函數和放大率目標函數--38
第四章、實驗結果與分析-------40
4-1 實驗環境------40
4-2 實驗結果------40
第五章、結論和未來研究方向----44
第六章、參考文獻---45

參考文獻

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指導教授

劉建男(Chien-Nan Liu)

審核日期

2017-5-3

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