用於類比電路仿真器的 波動數位濾波器架構之定點數實現方法

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：116

、訪客IP：18.217.45.29

姓名

劉如軒(Loo-Shean Liu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

用於類比電路仿真器的波動數位濾波器架構之定點數實現方法
(Fixed-Point Implementation of Wave Digital Filters for Analog Circuit Emulation)

相關論文

★ 用於類比電路仿真之波動數位濾波器架構的自動建構方法	★ 使用波動數位濾波器與非線性MOS模型的類比電路模擬平台
★ 實現波動數位濾波器架構下之類比仿真器的非線性電晶體模型	★ 以節點保留方式進行壓降分析中電源網路模型化簡的方法
★ 以引導式二階權重提取改進辨認二階臨界函數之研究	★ 以基本類比電路架構為基礎的佈局自動化工具
★ 可保留設計風格及繞線行為之類比佈局遷移技術	★ 自動辨識混合訊號電路中數位區塊之方法
★ 運用於記憶體內運算的SRAM功率模型之研究	★ 考量可繞度及淺溝槽隔離效應之類比佈局擺置微調方法
★ 一個適用於量化深度神經網路且可調整精確度的處理單元設計: 一種階層式的設計方法	★ 一個有效的邊緣智慧運算加速器設計: 一種適用於深度可分卷積的可重組式架構
★ 實現類比電路仿真的波動數位濾波器架構生成與模擬	★ 用於類比電路仿真器的波動數位濾波器之硬體最佳化方法
★ 自動辨識混合訊號電路中構成區塊及RLC元件之方法	★ 以波動數位濾波器實現類比電路仿真器所需的FPGA表格縮減技術

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

隨著製程進步，目前的超大型積體電路設計愈來愈複雜，單晶片系統( System on Chip , SOC ) 成為設計的選項之一，由於一個系統通常同時包含數位電路與類比電路，因此類比/混合訊號(Analog/mixed-signal, AMS)電路的驗證在開發晶片的流程中變的重要許多。在這篇論文中，我們採用波動數位濾波器(Wave Digital Filter, WDF)的原理，將類比電路轉成對應的數位電路來進行仿真。此方法使用入射波與反射波的方式描述電路特性，可以將每個類比元件對應至波動數位濾波器架構的數位元件，達成與數位電路一起模擬的目標。
本研究根據WDF架構仿真流程之相關文獻，開發硬體實現流程，建立仿真電路硬體架構，並實現於FPGA板上，使得整個仿真流程完整。也添加了定點數設計概念到硬體實現流程中來降低複雜度，並發展了定點數轉換流程。關於非線性的MOS元件，也成功以查表法的方式實作出來，解決了MOS元件數位化的問題。由實驗結果得知，定點數設計與浮點數設計的硬體資源使用率相當，準確度與HSPICE模擬波形相比，相關係數皆有在0.98以上，但於處理速度方面來說，定點數設計快浮點數約4倍多，因此相較於浮點數設計，定點數設計是個更加的選擇。

摘要(英)

With the advance of process technologies, the design of Very-Large-Scale Integration (VLSI) circuits is becoming more complex. System on Chip (SOC) has become one possible option of VLSI design. Because SOC designs usually contain both analog and digital circuits, it is important to have an Analog/Mixed-Signal (AMS) verification flow for chip development. In this thesis, we adopt Wave Digital Filter theory to map analog circuits into digital circuits for emulating analog circuits. This method uses incident and reflected waves to model circuit characteristics. Each analog component can be transformed into digital component in WDF framework to support the co-simulation with digital circuits.
Based on the relevant research of WDF emulation process, this thesis develops the hardware implementation flow to establish the hardware structure of the emulator. The whole emulator has been implemented on FPGA to verify the whole flow of WDF emulation. In addition, this thesis adopts the fixed-point design concept to the hardware implementation to reduce the complexity and develops fixed-point conversion flow. About the non-linear MOS components, we also successfully implement the table lookup approach on FPGA to solve the digitalization issue. According to the experimental results, the hardware resource usage of the fixed-point design and the floating-point design is similar. In terms of accuracy, the correlation coefficient of waveform between WDF and HSPICE is higher than 0.98. However, the processing speed of fixed-point design is more than 4 times than that of floating-point design. Therefore, compared to floating-point design, fixed-point design is an appropriate choice.

關鍵字(中)

★ 波動數位濾波器
★ 仿真
★ 定點數
★ 類比電路仿真器

關鍵字(英)

★ wave digital filiter
★ emulation
★ fixed-point
★ analog circuit emulator

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 ix
1 第一章、緒論 1
1-1 研究動機 1
1-2 相關研究 3
1-2-1 場列式可程式類比陣列(FPAA) 3
1-2-2 可程式化類比元件陣列(PANDA) 5
1-3 論文結構 7
2 第二章、背景知識 8
2-1 數位濾波器(Digital Filter)模型 8
2-2 波動數位濾波器(Wave Digital Filter) 10
2-2-1 波動數位濾波器模型 10
2-2-2 配線器(Adaptor) 13
2-2-3 非線性半導體場效電晶體模型(MOSFET) 17
2-2-4 新式J型配線器(J-type adaptor) 22
3 第三章、定點數硬體設計方法 25
3-1 類比仿真器的仿真流程 25
3-2 硬體實現平台 27
3-3 線性電路 31
3-3-1 電路元件與配線器 31
3-3-2 定點數轉換 40
3-3-3 仿真電路硬體實現 41
3-4 非線性半導體場效電晶體實作 44
4 第四章、實驗結果 46
4-1 實驗環境 46
4-2 線性RC電路 46
4-3 T型橋式電路(Bridge-T) 50
4-4 P型金氧半場效電晶體(PMOS) 53
4-4-1 定點數設計與浮點數設計 53
4-4-2 新式非線性模型與線性小訊號模型 57
5 第五章、結論與未來工作項目 61
6 參考文獻 62

參考文獻

[1] G. E. Moore, “Cramming More Components Onto Integrated Circuits,” Proceedings of the IEEE, Jan 1998.
[2] M. Vertregt, “The analog challenge of nanometer CMOS,” Int’l Electron Devices Meeting, pp.1-8, Dec. 2006
[3] Fettweis, “Wave digital filters: Theory and practice,” Proceedings of the IEEE, vol. 74, no. 2, pp. 270–327, 1986.
[4] K. Meerkotter and R. Scholz, “Digital simulation of nonlinear circuits by wave digital filter principles,” IEEE Int’l Symp. on Circuits and Systems, pp. 720–723, 1989.
[5] H. Kutuk and S.-M. Kang, “A field-programmable analog array (FPAA) using switched-capacitor techniques,” in Proc. IEEE Int’l Symp. on Circuits and Systems, vol. 4, 1996, pp. 41-44, 1996.
[6] E. K. Lee and W. L. Hui, “A novel switched-capacitor based field-programmable analog array architecture,” in Field-Programmable Analog Arrays, Springer, pp. 33-50, 1998.
[7] E. K. Lee and P. G. Gulak, “A transconductor-based field-programmable analog array,” in Proc. IEEE Int’l Solid-State Circuits Conf., pp. 198-199, 1995.
[8] B. Pankiewicz, M. Wojcikowski, S. Szczepanski, and Y. Sun, “A field programmable analog array for CMOS continuous-time OTA-C filter applications,” IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 125-136, 2002.
[9] T. S. Hall, C. M. Twigg, J. D. Gray, P. Hasler, and D. V. Anderson, “Large-scale field-programmable analog arrays for analog signal processing,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 52, no. 11, pp. 2298-2307, 2005.
[10] N. Suda & J. Suh & N. Hakim & Y. Cao & B. Bakkaloglu, “A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation,” IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 181-190, Jan 2016.
[11] D. Franken & J. Ochs & K. Ochs, ”Generation of Wave Digital Structures for Connection Networks Containing Ideal Transformers,” in Proc. IEEE Int. Symp. Circuits and System, vol.1, pp. III-240-III-243, June, 2003.
[12] Y.-S. Han, “A simulation platform for analog circuits using wave digital filters and Nonlinear MOS model,” National Central University, Taiwan, 2015.
[13] H.-P. Yang, “Automatic Construction and Scheduling of the Wave Digital Filter Structures for Analog Emulators,” National Central University, Taiwan, 2016.
[14] C.-H. Wang, “Nonlinear Transistor Model for WDF-Based Analog Emulators,” National Central University, Taiwan, 2016.
[15] S.A Dyer, J.S Dyer, “Cubic-spline interpolation. 1” IEEE Instrumentation & Measurement Magazine, vol. 4, no. 1, pp. 44-46
[16] H.-P. Yang, H.-J. Hsu, C. Wang, C.-N. J. Liu, and J.-Y. Jou, “Automatic Netlist Transformation for WDF-Based Analog Emulator,” Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), Oct. 2016.
[17] W. Wu, Y.-L. Chen, Y. Ma, C.-N. Liu, J.-Y. Jou, S. Pamarti, and L. He, “Wave Digital Filter based Analog Circuit Emulation on FPGA,” IEEE Int’l Symp. on Circuit and Systems, May 2016.
[18] S.-Y. Pan, ”A New Adaptor for WDF-Based Analog Emulator with Complicated Topology,” National Central University, Taiwan, 2017
[19] T. Schwerdtfeger and A. Kummert, “A Multidimensional Signal processing approach to WDF with topology-related delay-free loops,” IEEE Int’l Conf. on Acoustics, Speech and Signal Processing (ICASSP), 2014.
[20] Xilinx, Inc., “Zynq-7000 All Programmable SoC Overview,” 2016 [Online].Available:https://www.xilinx.com/support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf
[21] M.-Y. Li, ”Hardware Implementation of Analog Emulator Based on Wave Digital Filters,” National Central University, Taiwan, 2017
[22] Department of Radio Engineer, Czech Technical University, “Quantization and Quantized Filtering (Filter Design Toolbox),” 2017[Online].Available: http://radio.feld.cvut.cz/matlab/toolbox/filterdesign/quant14a.html
[23] B. J. Sheu, D. L. Scharfetter, P.-K. Ko, and M.-C. Jeng, “Bsim: Berkeley short-Channel IGFET model for MOS transistors,” IEEE J. Solid-State Circuits, vol. 22, no. 4, pp. 558–566, 1987.
[24] T. Shima, T. Sugawara, S. Moriyama, and H. Yamada, “Three-dimensional table look-up MOSFET model for precise circuit simulation,” IEEE J. Solid-State Circuits, vol. 17, no. 3, pp. 449-454, 1982.
[25] A. Sarti and G. D. Poli, “Toward Nonlinear Wave Digital Filters,” IEEE Trans. on Signal Processing, vol. 47, no. 6, pp. 1654-1668, 1999.

指導教授

周景揚(Jing-yang Jou)

審核日期

2017-8-18

推文