博碩士論文 103521111 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:57 、訪客IP:3.145.19.0
姓名 陳修銘(Shiou-Ming Chen)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 評估任意比值陣列區塊電容不匹配效應之矩陣分析法
(Matrix Analysis for Mismatching of General Ratio Block Capacitances)
相關論文
★ E2T-iSEE:應用於事件與情感狀態轉移排程器之編輯★ “偶”:具情感之球型機器人
★ 陣列區塊電容產生器於製程設計套件之評量★ 應用於數位家庭整合計畫影像傳輸子系統之設計考量與實現
★ LED 背光模組靜電放電路徑★ 電阻串連式連續參考值產生器於製程設計套件之評量
★ 短篇故事分類與敘述★ 延伸考慮製程參數相關性之類比電路階層式變異數分析器
★ 以電子電路觀點對田口式惠斯登電橋模擬實例的再分析★ 應用於交換電容ΔΣ調變電路之電容排列良率自動化擺置平台
★ 陣列MiM電容的自動化佈局★ 陣列MiM電容的平衡接點之通道繞線法
★ 氣象資訊達人★ 嵌入式WHDVI多核心Forth微控制器之設計
★ 應用於電容陣列區塊之維持比值良率的通道繞線法★ 使用於矽穿孔耦合分析之垂直十字鏈基板結構
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 ( 永不開放)
摘要(中) 積體電路隨著製程的精進與微縮,元件尺寸持續下探到物理極限,為我們帶來體積更小、效率更高的電子設備。但是隨之而來的卻是更艱難的製程要求和更嚴重的非理想效應,造成產品的良率下降,影響成本與品質。
電容是積體電路中重要的被動元件之一,在許多類比電路中,需要精確的電容值來實現正確的電路功能,隨著元件到達數奈米等級的製程,半導體設備運行中所遇到的隨機變動,對電容參數的影響更甚以往,若無採取適當的對策,甚至會造成電路失效。因此對於設計者而言,如何在設計階段就能評估電路抵抗製程變動能力,將是決定最後產品良率的關鍵。
本論文針對兩任意比例的電容陣列所遇到的隨機與系統性變動,推導出矩陣形式的分析法評估其對單位電容陣列的影響,並且得以加入多種系統變動與各種擺放形式做出交叉評估,最後採用matlab統計分析軟體來模擬各種情境下兩電容陣列的不匹配程度,並用實例來驗證和說明分析結果。
摘要(英) The integrated circuit has become more and more sophisticated, moreover, the feature size of device is shrunk to the physical limit. Smaller circuit brings the more efficient electronic product. However, the attendant problem on complex technology is strict quality and critical non-ideal effect of semiconductor that reduces the yield of product, quality and rises the cost.
Capacitance is the one of the most important passive device in the circuit. In the analog circuit, the correct function is dominated by the accuracy value of capacitance. With the components to reach the number of nano-level process, the random mismatch of the equipment will acutely affect the parameter of capacitance during the step of process.
Without an appropriate strategy, the mismatching device will fail the circuit if worse coming to worst. For the designer, how to evaluate the performance of circuit to tolerate the process variation at the step of layout is the key point of reliable chip.
This thesis research the mismatch of two general-ratio block capacitance with random and systematic variation. We derive the matrix analysis for estimating the mismatch of two unit-capacitance arrays. Furthermore, we consider the common systematic variation and placement into the matrix analysis. Finally, we use the matlab and case to verify the result of mismatch with process variation.
關鍵字(中) ★ 電容
★ 不匹配
關鍵字(英) ★ Capacitors
★ Mismatch
論文目次 摘要 I
Abstract II
Chapter 1. 緒論 - 1 -
1.1 研究動機 - 1 -
1.2 論文架構 - 2 -
Chapter 2. 電容與設計原則 - 3 -
2.1 電容之簡介 - 3 -
2.2 電容的不匹配 - 7 -
2.3 匹配電容的設計原則 - 8 -
Chapter 3. 電容擺放方法與變異量化 - 12 -
3.1 共質心(Common-Centroid)擺放原則 - 12 -
3.2 分析統計原理 - 15 -
3.3 空間相關性(Spatial correlation) - 17 -
3.4 量化不匹配(Mismatch)程度 - 19 -
3.5 不匹配與相關係數 - 20 -
Chapter 4. 矩陣分析法 - 22 -
4.1 雙目標(Two-Target)電容不匹配的矩陣形式 - 22 -
4.2 系統性變動之特徵矩陣 - 23 -
4.3 平移(Offset)與梯度(Gradient)效應 - 23 -
4.4 任意比值(General-Ratio)電容的不匹配 - 26 -
4.5 固定變異係數與標準差下的不匹配 - 29 -
4.6 案例分析:擺放方式對不匹配的影響 - 31 -
4.7 案例分析:CMP效應─採用曼哈頓距離分析 - 34 -
Chapter 5. 結論 - 38 -
參考文獻 - 39 -
參考文獻 [1] P. W. Luo, J. E. Chen, C. L. Wey, L. C. Cheng, J. J. Chen and W. C.Wu,“ Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 2097-2101, Nov.2008.
[2] C. W. Lin, J. M. Lin, Y. C. Chiu, C. P. Huang, S. J. Chang, ” Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits” Design Automation Conference (DAC), 2011
[3] D. Khalil and M. Dessouky. “Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio,” Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pp. 576-580, Mar. 2002.
[4] B. Razavi, Design of Analog CMOS Integrated Circuits, Mcgraw-Hill,2001.
[5] J. E Chen, P. W. Luo, C. L. Wey, “Yield evaluation of analog placement with arbitrary capacitor ratio” Quality of Electronic Design, ISQED, 2009
[6] C. C. Huang, J. E Chen, P. W. Luo, C. L. Wey “Yield-award placement optimization for Switched-Capacitor analog integrated circuits” SOC Conference (SOCC), 2011
[7] M. J. McNutt, S. LeMarquis, and J. L. Dunkley,“ Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE Journal Solid-State Circuits, pp. 611-616, May1994.
[8] C. S. G. Conroy, W. A. Lane, and M. A. Moran, “Statistical Design Techniques for D/A Converters,” IEEE Journal of Solid-State Circuits, pp. 1118-1128, Aug 1989.
[9] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, pp. 1433-1439, Oct 1989
[10] L. Zhang, R. Raut, Y. Jiang, and U. Kleine. “Placement algorithminanalog-layout designs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp.1889–1903, Oct.2006.
[11] P. W. Luo, J. E. Chen, C. L. Wey, “Placement Optimization for Yield Improvement of Switched-Capacitor AnalogIntegratedCircuits ”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No.2, pp. 313-318, Feb.2010.
[12] Y. Li, et. al.. “Placement for Binary-Weighted Capacitive Array in SAR ADC Using Multiple Weighting Methods,” IEEE TCAD 2014.
[13] CC Huang, et. al., “PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays ,” IEEE TCAD 2016
[14] X. Jinjun, V. Zolotov, and H. Lei, “Robust Extraction of Spatial Correlation,”IEEETrans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 193-202, Apr.2007.
[15] A. Stuart and J. K. Ord, Kendall’s “Advanced Theory of Statistics, 5th ed”.,vol. 1. New York: Oxford Univ. Press, 1987, pp. 320–325
[16] 林厚運, 「應用於類比積體電路中評估二相同比值陣列區塊電容不匹配效應的矩陣性質解析法」,中央大學電機工程系碩士論文,2011
[17] 楊志嘉, 「陣列區塊排列之比率不匹配的性能指標」,中央大學電機工程系碩士論文,2016
指導教授 陳竹一(Jwu-E Chen) 審核日期 2017-10-25
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明