將戴爾他電路模型應用於類比電路的製程變異及老化效應分析之研究

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阮貴曹(Nguyen Cao Qui) 查詢紙本館藏

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電機工程學系

論文名稱

將戴爾他電路模型應用於類比電路的製程變異及老化效應分析之研究
(On the Applications of Delta Circuit Model for the Analysis of Process Variation and Aging Effects in Analog Circuits)

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摘要(中)

隨著積體電路製程尺寸越來越小，製程變異和老化效應對類比電路的良率及可靠度的影響也越來越大，如果設計的初期就能把這些非理想效應考慮進去，就可以大幅降低重新設計所需的成本。在傳統以模擬為基礎的解決方案中，雖然可以達到較高的精準度，但模擬所需的時間和代價卻非常高昂。因此，我們提出了一種新的模擬分析方法，可以同時考慮製程變異和老化效應，並在維持高精準度的前提之下，將模擬所需的資源降至合理的範圍。

首先，我們使用一組改進過的戴爾他元件模型來進行電路模擬，由這些元件所組成的戴爾他電路模型，可以藉由動態步階控制的原理，自動提升暫態分析的模擬速度。為了進一步提高效率，本論文提出了一種叢集式戴爾他QMC模擬技術，有效結合了戴爾他電路模型以及QMC取樣，以減少每個樣本的增量變化。由實驗結果可知，我們提出的方法可以將模擬速度提高兩個數量級，並具有幾乎相同的準確度，明顯的提高了良率分析的效率。

其次，本論文利用戴爾他模型為基礎，提出了一種漸進式的模擬技術，可以加快電路老化的模擬速度，並保有其原本的精準度，因為電路老化通常是一個緩慢變化的過程，我們提出的漸進式方法可以有效降低模擬的時間。而且，因為在蒙地卡羅的良率分析中，每一個樣本基本上都是相同的電路，只是參數有一些微小的差異，因此，對於效能衰退後的電路，我們也可以用漸進式的技術有效降低良率分析的時間。再加上我們提出的動態老化取樣技術，可以讓整體的模擬速度在最大估計誤差為1%時加速近五十倍，並且幾乎沒有損失精準度，有效地提升電路壽命分析的效率。

摘要(英)

As devices continue to shrink, the process variation and aging effects have increasing impacts on the circuit yield and reliability, particularly for analog circuits. If those non-ideal effects can be considered in early design stages, the re-design and re-spin costs can be significantly reduced. Traditional simulation-based methods to deal with the problems can achieve a high accuracy, but the simulation cost is very expensive. Thus, a new simulation-based analysis method that considers the process variation and aging effects is proposed, which can keep the cost at a reasonable scale while maintaining high accuracy.

First, the delta circuit model is improved with a set of basic delta devices for circuit simulation. By using the delta circuit model, simulation speed can be improved automatically due to the dynamic step control in transient analysis. In order to further improve the efficiency while combining the delta circuit model and QMC sampling, a cluster-based delta-QMC technique is proposed in this dissertation to reduce the delta change in each sample. Experimental results indicate that the proposed approach can increase simulation speed by two orders of magnitude with almost the same accuracy, which significantly improves the efficiency of yield analysis.

Second, an incremental simulation technique based on delta model is proposed to improve the simulation speed of lifetime yield analysis while maintaining the analysis accuracy. Because aging is often a gradual process, the proposed incremental technique is effective for reducing the simulation time. For yield analysis with degraded performance, this incremental technique also reduces the simulation time because each sample is the same circuit with small parameter changes in the Monte Carlo analysis. When the proposed dynamic aging sampling technique is employed, 50X speedup can be obtained with maximum estimation error of 1%, which considerably improves the efficiency of lifetime yield analysis.

關鍵字(中)

★ 三角洲电路模型

關鍵字(英)

★ delta circuit model
★ lifetime yield reliability analysis
★ variation analysis
★ Monte Carlo Simulation
★ QMC
★ Yield Analysis

論文目次

摘要 i
Abstract ii
Acknowledgment iii
Table of Contents iv
List of Figure vii
List of Tables ix
Acronyms x
Notation Illustration xi
Chapter 1 Introduction 1
1.1 The Analog IC Design Flow 1
1.2 Computer-Aided Design Tools for Analog Design 3
1.2.1 Circuit Simulation 6
1.2.2 Behavior Models 6
1.2.3 Topology Selection 7
1.2.4 Device Sizing 8
1.2.5 Layout Implementation 9
1.3 Process Variation and Reliability Issues 9
1.3.1 Process Variations 11
1.3.2 Aging Effects 14
1.4 Motivation 18
1.5 Organization 20
Chapter 2 Delta Devices and Delta Circuits 21
2.1 Signal Speed and Simulation Time 21
2.2 Linear Delta Devices 22
2.2.1 Delta Resistor 24
2.2.2 Delta capacitor and delta inductor 24
2.3 Previous Delta Models for Nonlinear Devices 25
2.4 Proposed Delta Models for Nonlinear Devices 26
2.4.1 Delta Dependent Sources 26
2.4.2 Delta Nonlinear Resistor, Capacitor and Inductor 27
2.4.3 Delta Diode 28
2.4.4 Delta MOSFET 29
2.5 Proposed Approach to Construct a Delta Circuit 30
2.6 Experimental Results 32
2.6.1 Experimental Setup 32
2.6.2 Results of the Inverter 32
2.6.3 Results of Second-Order Low-Pass Filter 34
2.7 Summary 37
Chapter 3 Cluster-Based Delta-QMC Technique for Yield Analysis 38
3.1 Background 38
3.1.1 Yield and Loss 38
3.1.2 Monte Carlo Method 38
3.1.3 Quasi Monte Carlo Method 39
3.1.4 Sobol points 40
3.1.5 Variance of QMC Method 41
3.2 Delta-QMC Techniques for MC Analysis 42
3.2.1 Delta-QMC simulation 42
3.2.2 Cluster-based delta-QMC Simulation 44
3.3 Experimental Results 49
3.3.1 Experimental Setup 49
3.3.2 Results of The Bandgap Reference 49
3.3.3 Results of The 64-bit SRAM 52
3.4 Summary 54
Chapter 4 Incremental Lifetime Yield Analysis Based on Delta Model 54
4.1 Transistor Aging Effects 54
4.2 Reviews of Reliability Simulators 57
4.1.1 Berkeley Reliability Tool (BERT) 57
4.1.2 RelXpert 58
4.1.3 Eldo Aging Simulator 59
4.3 The Related Works of Lifetime Yield Analysis 60
4.4 Incremental Lifetime Yield Analysis 62
4.4.1 Proposed Lifetime Yield Analysis Flow 63
4.4.2 Dynamic Aging Sampling 65
4.4.3 MC Simulations with Delta Circuit Models 66
4.5 Experimental Results 68
4.5.1 Experimental Setup 68
4.5.2 Results of Two-Stage NMOS Amplifier 69
4.5.3 Results of The Bandgap Reference 71
4.6 Summary 72
Chapter 5 Conclusions and Future Works 74
Reference 76
Publication List 87

參考文獻

[1] R. A. Rutenbar, “Design Automation for Analog: The Next Generation of Tool Challenge,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), paper 458-460, November 2006.
[2] G. G. E. Gielen and R. A. Rutenbar , “Computer-Aided Design of Analog and Mixed-Signal Integrated Circuits,” Proceedings of the IEEE, volume 88, number 12, pages 1825-1852, December 2000.
[3] R. A. Rutenbar, “Design Automation for Analog: The Next Generation of Tool Challenge,” in Proceedings of IBM Academy Conference, April 2006.
[4] HSPICE user guide: Simulation and analysis, Version A-2008.03, Synopsys Inc., March 2008.
[5] Medhat Karam, Wael Fikry, Hani Ragai, “Implementation of hot-carrier reliability simulation in Eldo,” in Proceedings of IEEE International Symposium on Circuit and System (ISCS), pages 515-518, May 2001.
[6] K. O. Kundert, The designer’s guide to SPICE and SPECTRE, Norwell, Massachusetts: Kluwer, pages 129-249, 1995.
[7] F. Gong, H. Yu, Y. Shi, D. Kim, J. Ren, and L. He, “QuickYield: An efficient global-search based parametric yield estimation with performance constraints,” in Proceedings of IEEE/ACM Design Automation Conference (DAC), pages 392–397, June 2010.
[8] H. Forghani-Zadeh and G. Rincon-Mora, “Fast And Reliable Top-Level Simulation Strategy For Mixed-Signal Integrated Circuits And Its Application to DC-DC Converters,” IET Circuits, Devices Systems, volume 1, number 2, pages 143–150, April 2007.
[9] G. Ruan, J. Vlach, J. Barby, and A. Opal, “Analog Functional Simulator For Multilevel Systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 10, number 5, pages 565–576, May 1991.
[10] J. Besnard, J. Benkoski, and B. Hennion, “Eldo-XL: A Software Accelerator For The Analysis Of Digital MOS Circuits By An Analog Simulator,” in Proceedings of the European Conference on Design Automation (EDAC), February 1991.
[11] S. Nyati, C. A. Wegner, R. W. Delmerico, R. J. Piwko, D. H. Baker, and A. Edris, “Effectiveness of thyristor controlled series capacitor in enhancing power system dynamics: an analog simulator study,” IEEE Transactions on Power Delivery, volume 9, number 2, pages 1018–1027, Apr 1994.
[12] Y. Sugimoto, “A Highly Efficient Transient And Frequency-Response Simulation Method For Switching Converters Without Using A SPICE-Like Analog Simulator,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pages 1308–1311, May 2010.
[13] A. Mounir, A. Mostafa, and M. Fikry, “Automatic Behavioural Model Calibration For Efficient PLL System Verification,” in Proceedings of IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE), pages 280–285, March 2003.
[14] S. Tan, W. Guo, and Z. Qi, “Hierarchical Approach to Exact Symbolic Analysis of Large Analog Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 24, number 8, pages 1241–1250, August 2005.
[15] E. S. J. Martens and G. G. E. Gielen, “Analyzing Continuous-time Delta; Sigma; Modulators with Generic Behavioral Models,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 25, number 5, pages 924–932, May 2006.
[16] C.-C. Kuo, M.-J. Lee, C.-N. Liu, and C.-J. Huang, “Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models,” IEEE Transactions on Circuits and Systems I: Regular Papers, volume 56, number 6, pages 1160–1172, June 2009.
[17] F. Gong, S. Basir-Kazeruni, L. He, and H. Yu, “Stochastic Behavioral Modeling and Analysis for Analog/Mixed-Signal Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 32, number 1, pages 24–33, January 2013.
[18] P. Veselinovic et al., “A flexible topology selection program as part of an analog synthesis system,” in Proceedings of IEEE European Design Test Conference (ED&TC), pages 119–123, March 1995.
[19] R. Harjani and J. Shao, “Feasibility and performance region modeling of analog and digital circuits,” Kluwer International Journal on Analog Integrated Circuits and Signal Processing, volume 10, pages 23–43, January 1996.
[20] P. Maulik, L. R. Carley, and R. Rutenbar, “Simultaneous topology selection and sizing of cell-level analog circuits,” IEEE Transactions on Computer-Aided Design, volume 14, pages. 401–412, April 1995.
[21] Z. Ning et al., “SEAS: A simulated evolution approach for analog circuit synthesis,” in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 5.2.1–5.2.4, May 1991.
[22] W. Kruiskamp and D. Leenaerts, “DARWIN: CMOS opamp synthesis by means of a genetic algorithm,” in Proceedings of ACM/IEEE Design Automation Conferences. (DAC), pages 550–553, June 1995.
[23] C.-W. Lin, P.-D. Sue, Y.-T. Shyu, and S.-J. Chang, “A Bias-Driven Approach for Automated Design of Operational Amplifiers,” in Proceedings of International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pages 118–121, April 2009.
[24] R. Phelps, M. Krasnicki, R. Rutenbar, L. Carley, and J. Hellums, “Anaconda: Simulation-Based Synthesis of Analog Circuits Via Stochastic Pattern Search,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 19, number 6, pages 703–717, June 2000.
[25] M. Hershenson, S. Boyd, and T. Lee, “Optimal Design of A CMOS OpAmp Via Geometric Programming,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 20, number 1, pages 1–21, January 2001.
[26] W. Gao and R. Hornsey, “A Power Optimization Method for CMOS Op-Amps Using Sub-Space Based Geometric Programming,” in Proceedings of IEEE Design, Automation Test in Europe Conference Exhibition (DATE), pages 508–513, March 2010.
[27] P.-H. Lin, Y.-W. Chang, and S.-C. Lin, “Analog Placement Based on Symmetry-Island Formulation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 28, number 6, pages 791–804, June 2009.
[28] Y.-P. Weng, H.-M. Chen, T.-C. Chen, P.-C. Pan, C.-H. Chen, and W.-Z. Chen, “Fast Analog Layout Prototyping for Nanometer Design Migration,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 517–522, November 2011.
[29] P.-Y. Chou, H.-C. Ou, and Y.-W. Chang, “Heterogeneous B∗-trees for analog placement with symmetry and regularity considerations,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 512–516, November 2011.
[30] L. Xiao, E. Young, X. He, and K. P. Pun, “Practical Placement and Routing Techniques for Analog Circuit Designs,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 675–679, November 2010.
[31] R. Wilcox, T. Forhan, G. Starkey, and D. Turner, “Design for Manufacturability: A Key to Semiconductor Manufacturing Excellence,” in Proceedings of IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, pages 308–313, September 1998.
[32] M. Buhler, J. Koehl, J. Bickford, J. Hibbeler, U. Schlichtmann, R. Sommer, M. Pronath, and A. Ripp, “DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield - Influence of Process Variations in Digital, Analog and Mixed-Signal Circuit Design,” in Proceedings of IEEE Design, Automation and Test in Europe (DATE), pages 1–6, March 2006.
[33] M. Mounir Mahmoud, N. Soin, and H. Fahmy, “Design Framework to Overcome Aging Degradation of the 16nm VLSI Technology Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 33, number 5, pages 691–703, May 2014.
[34] S. Lamont, “Automated Design For DFM/DFY,” in Proceedings of IBM Academy Conference, April 2005.
[35] D. Sylvester, K. Agarwal, and S. Shah, "Variability in nanometer CMOS: Impact, analysis, and minimization," Integration, the VLSI Journal, Elsevier, volume 41, pages 319-339, May 2008.
[36] K. Kuhn, “Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS,” in Proceedings of IEEE International Electron Devices Meeting (IEDM), pages 471–474, December 2007.
[37] B. P. Wong, Nano-CMOS Circuit and Physical Design, New Jersey John Wiley, 2005.
[38] D. Boning and S. Nassif, "Models of Process Variations in Device and Interconnect," in Design of High-Performance Microprocessors Circuits, 1st edition, pages 98-116, Wiley-IEEE Press, 2000.
[39] D. Hocevar, M. Lightner, and T. Trick, “A study of variance reduction techniques for estimating circuit yields,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 2, number 3, pages 279–287, March 1983.
[40] J. Jaffari and M. Anis, “On efficient LHS-based yield analysis of analog circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 30, number 1, pages 159–163, January 2011.
[41] M. McKay, R. Beckman, and W. Conover, “A comparison of three methods for selecting values of input variables in the analysis of output from a computer code,” Technometrics, Taylor & Francis, volume 21, number 2, pages 239–245, May 1979.
[42] A. Singhee and R. Rutenbar, “From finance to flip flops: A study of fast quasi-Monte Carlo methods from computational finance applied to statistical circuit analysis,” in Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 685-692, March 2007.
[43] A. Singhee and R. Rutenbar, “Statistical blockade: Very fast statistical simulation and modeling of rare circuit events and its application to memory design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 28, number 8, pages 1176–1189, August 2009.
[44] A. Bayrakci, A. Demir and S. Tasiran “Fast Monte Carlo estimation of timing yield with importance sampling and transistor-level circuit simulation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 29, number 9, pages 1328–1341, August 2010.
[45] S. Vrudhula, J. Wang, and P. Ghanta, “Hermite polynomial based interconnect analysis in the presence of process variations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 25, number 10, pages 2001–2011, October 2006.
[46] X. Li, J. Le, P. Gopalakrishnan, and L. Pileggi, “Asymptotic probability extraction for nonnormal performance distributions,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 26, number 1, pages 16–37, January 2007.
[47] R. Krishnan, W. Wu, F. Gong, and L. He, “Stochastic behavioral modeling of analog/mixed-signal circuits by maximizing entropy,” in Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 572–579, March 2013.
[48] FineSim™, Synosys Inc., http://www.synopsys.com/Tools/ Verification/ AMSVerification/Pages/finesim-ds.aspx.
[49] UltraSim®, Cadence Design Systems Inc., http://www.cadence.com/ products/cic/UltraSim_fullchip.
[50] X. Li, J. Le, L.T. Pileggi, and A. Strojwas, “Projection-based performance modeling for inter/intra-die variations”, in Proceedings of International Conference on Computer-Aided Design (ICCAD), pages 721-727, November 2005.
[51] T.-K. Yu, S. M. Kang, I. N. Hajj, and T. N. Trick, “Statistical performance modeling and parametric yield estimation of MOS VLSI,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 6, number 6, pages 1013–1022, November 1987.
[52] E. Felt, S. Zanella, C. Guardiani, A. Sangiovanni-Vincentelli, “Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling”, in Proceedings of International Conference on Computer-Aided Design (ICCAD), pages 374-380, November 1996.
[53] Y. Cao, and L. T. Clark, “Mapping statistical process variations toward circuit performance variability: an analytical modeling approach”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 26, pages 1866-1873, October 2007.
[54] Y.-L. Chen, W. Wu, C.-N. J. Liu, and L. He, “Incremental Latin Hypercube Sampling for Lifetime Stochastic Behavioral Modeling of Analog Circuits,” in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 556-561, January 2015.
[55] D. K. Schroder and J. A. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing,” Journal of Applied Physics, volume 94, number 1, pages. 1–18, July 2003.
[56] K.-L. Chen, S. A. Saller, I. A. Groves, and D. B. Scott, “Reliability effects on MOS transistors due to hot-carrier injection,” IEEE Transactions on Electron Devices, volume ED-32, number 2, pages 386–393, February 1985.
[57] H.-J. Lee, K.-K. Kim, “Analysis of time dependent dielectric Breakdown in Nanoscale CMOS Circuit,” in Proceedings of International SoC Design Conference (ISOCC), pages 440-443, November 2011.
[58] J. Black, “Electromigration—A brief survey and some recent results,” IEEE Transactions on Electron Devices, volume 16, number 4, pages 338-347, April 1969.
[59] S. Han, B-S. Kim, and J. Kim, “Variation-aware aging analysis in digital ICs,” IEEE Transactions on VLSI Systems, volume 21, number 12, pages 2214-2225, December 2013.
[60] W. Wang, S. Yang, S. Bhardwaj, S. Vrudhula, F. Liu, and Y. Cao, “The impact of NBTI effect on combinational circuit: Modeling, simulation, and analysis,” IEEE Transactions on VLSI Systems, volume 18, number 2, pages 173-183, February 2010.
[61] A. W. Strong, Reliability Wearout Mechanisms in Advanced CMOS Technologies, New York: Wiley, 2006.
[62] R. T. Hu, et. al., “Berkeley Reliability Tools-BERT,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 12, number 10, pages 1524-1534, October 1993.
[63] Cadence Design Systems, “Reliability simulation in integrated circuit design,” white paper, http://www.cadence.com/whitepapers/ 5082_Reliability_FNL_WP
[64] F. Marc, B. Mongellaz, C. Bestory, H. Levi, and Y. Danto, “Improvement of aging simulation of electronic circuits using behavioral modeling,” IEEE Transactions on Device and Materials Reliability, volume 6, number 2, pages 228–234, June 2006.
[65] Maricau, E. Gielen, “Efficient reliability simulation of analog ICs including variability and time-varying stress,” in Proceedings of IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE), pages 1238–1241, April 2009.
[66] C. Bestory, F. Marc, and H. Levi, “Statistical analysis during the reliability simulation,” Microelectronics Reliability, Elsevier, volume 47, number 9–11, pages 1353–1357, September 2007.
[67] X. Pan and H. Graeb, “Lifetime yield optimization of analog circuits considering process variations and parameter degradations,” Advances in Analog Circuits, pages 131-142, InTech, Rijeka , 2011.
[68] X. Pan and H. Graeb, “Reliability analysis of analog circuits using quadratic lifetime worst-case distance prediction,” in Proceedings of Custom Integrated Circuits Conference (CICC), pages 1559–1564, September 2012.
[69] Y.-L. Chen, W.-R. Wu, and C.-N. J. Liu, “Simultaneous optimization of analog circuits with reliability and variability for applications on flexible electronics,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 33, number 1, January 2014.
[70] T. Y. Zhou, Hang Liu, Dian Zhou and Tuna Tarim, “A fast analog circuit analysis algorithm for design modification and verification,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 30, number 2, pages. 308-313, February 2011.
[71] Manual: BSIM4.5 MOSFET model, University of California, Berkeley, 2005.
[72] Manual: MOSFET models, Version A-2008.03, Synopsys Inc., Mar. 2008.
[73] W. Zhao and Y. Cao, “New generation of predictive technology model for sub-45 nm early design exploration,” IEEE Transactions on Electron Devices, volume 53, number 11, pages 2816–2823, November 2006.
[74] I. M. Sobol, “The distribution of points in a cube and the approximate evaluation of integrals (English translation),” USSR Computational Mathematics and Mathematical Physics, volume 7, number 4, pages 86–112, 1967.
[75] A. Singhee and R. Rutenbar, “Why Quasi-Monte Carlo is better than Monte Carlo or Latin Hypercube Sampling for statistical circuit analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 29, number 11, pages 1763–1776, November 2010.
[76] P. Bratley and B. L. Fox, “Algorithm 659: Implementing Sobol’s quasirandom sequence generator,” ACM Transactions on Mathematical Software, volume 14, number 1, pages 88–100, 1988.
[77] S. Joe and F. Y. Kuo, “Remark on algorithm 659: Implementing Sobol’s quasirandom sequence generator,” ACM Transactions on Mathematical Software, number 1, pages 49–57, 2003.
[78] A. B. Owen, “Randomly permuted (t, m, s)-nets and (t, s)-sequences,” in Monte Carlo and Quasi-Monte Carlo Methods in Scientific Computing, pages 299–317, Springer, 1995.
[79] R. V. Hogg and A. T. Craig, Introduction to mathematical statistics, 3rd edition, Macmillan, 1971.
[80] D. G. Bonett and T. A. Wright, “Sample size requirements for estimating Pearson, Kendall and Spearman correlations,” Psychometrika, Springer, volume 65, number 1, pages. 23-28, March 2000.
[81] W. Wang, V. Reddy, A. T. Krishnan, R. Vattikonda, S. Krishnan and Y. Cao, “Compact modeling and simulation of circuit reliability for 65nm CMOS technology,” IEEE Transactions on Device and Materials Reliability, volume 7, number 4, pages 509-517, 2007.
[82] M. A. Alam and S. Mahapatra, “A comprehensive model of PMOS NBTI degradation,” Microelectronic Reliability, Elsevier, volume 45, number 1, pages 71–81, January 2005.
[83] S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, and S. Vrudhula, “Predictive modeling of the NBTI effect for reliable design,” in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 189–192, September 2006.
[84] S. Mahapatra, D. Saha, D. Varghese, and P. B. Kumar, “On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress,” IEEE Transactions on Electron Devices, volume 53, number 7, pages 1583–1592, July 2006.
[85] R. Shringarpure, S. Venugopal, Z. Li, L. Clark, D. Allee, E. Bawolek, and D. Toy, “Circuit Simulation of Threshold-Voltage Degradation in a-Si:H TFTs Fabricated at 175C,” IEEE Transactions on Electron Devices, volume 54, number 7, pages 1781–1783, July 2007.
[86] E. Maricau and G. Gielen, “Computer-Aided Analog Circuit Design for Reliability in Nanometer CMOS,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, volume 1, number 1, pages 50–58, March 2011.
[87] T. McConaghy and G. G. E. Gielen, “Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 28, number 11, pages 1627–1640, November 2009.
[88] NIMO Group, “Predictive technology model,” ASU, http://ptm.asu.edu/, accessed Sep. 03. 2016.
[89] D. Neamen, “Basic FET amplifiers,” in Microelectronics Circuit Analysis and Design, 4th edition, pages 205-284, McGraw-Hill, 2009.
[90] R. J. Baker, “Voltage references,” in CMOS Circuit Design, Layout and Simulation, 2nd edition, pages 745-772, Wiley Interscience, 2004.

指導教授

劉建男(Chien-Nan Liu)

審核日期

2017-12-21

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