W頻帶40奈米金氧半場效應電晶體低雜訊放大器暨Ka頻帶砷化鎵功率放大器之研製

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簡子涵(Tzu-Han Chien) 查詢紙本館藏

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電機工程學系

論文名稱

W頻帶40奈米金氧半場效應電晶體低雜訊放大器暨Ka頻帶砷化鎵功率放大器之研製
(Design of 40nm CMOS W-band Low Noise Amplifier and GaAs Ka-band Power Amplifier)

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摘要(中)

本論文設計研製收發機前端之低雜訊放大器及功率放大器，包含兩個W頻帶的低雜訊放大器及三個Ka頻帶的功率放大器。第二章首先使用TSMC 40nm General Purpose CMOS前瞻製程設計三級疊接低雜訊放大器，因其平行版式電容容值因製程變異改變巨大，達到60.8%，改版後將電容設計改成指叉式減少容值改變，亦使用分佈式電容為直流旁路電容。量測時，電流為模擬的三倍，亦將架構改成共源極以減少其功率消耗。實現一六級共源極低雜訊放大器，小訊號增益達到21.6 dB，3 dB頻寬為87~100.6 GHz，頻率在87及97 GHz時有最小雜訊指數7 dB，增益頻寬積為163.5 GHz，晶片面積為0.56 mm2。
第三章使用穩懋 0.15 μm InGaAs製程設計一個Ka頻帶雙功率整合功率放大器，使用雙整合技術來作功率整合，第一級增益單元串聯一組RC並聯來改善穩定度，第二級則兩兩電晶體合併，共合併四顆電晶體，輸出匹配電容較小故設計指叉式電容以因應小電容易受製程變異影響之特性。另介紹放大器穩定度檢查電路，除了檢查單級放大器的K值，檢查多級放大器穩定度時作級間穩定度模擬，以及檢查大功率電路穩定度的非線性穩定度模擬。其量測得小訊號增益13.9 dB，輸入1 dB增益壓縮點(IP1dB)約為5 dBm，而輸出1 dB增益壓縮點(OP1dB)約為17.7 dBm，飽和功率(Psat) 為24 dBm，功率消耗為1518 mW，晶片面積為4.6 mm2。
在第四章，我們分析疊接架構，推導其共閘極電晶體之閘極旁路電容容值，並設計兩種不同佈局方式的疊接放大器。其量測結果分別為，疊接一功率放大器，小訊號增益4.5 dB，輸入1 dB增益壓縮點(IP1dB)約為16 dBm，而輸出1 dB增益壓縮點(OP1dB)約為17.8 dBm，飽和功率(Psat) 為18 dBm，功率消耗為765 mW。疊接二功率放大器，小訊號增益5.2 dB，輸入1 dB增益壓縮點(IP1dB)約為17 dBm，而輸出1 dB增益壓縮點(OP1dB)約為19.3 dBm，飽和功率(Psat) 為19.5 dBm，功率消耗為740 mW。

摘要(英)

In this paper, we introduce the design of low noise amplifiers (LNA) and power amplifiers (PA). Including two w-band low noise amplifiers, and three ka-band power amplifiers. First, a w-band cascode three stages LNA using TSMC 40nm General Purpose CMOS process is presented, because the parallel capacitor varied greatly up to 60.8% by process varation. The interdigitated capacitor is used in the next version to prevent capacitance changing. The construction is changed from cascode three stages to common source (CS) six stages to improve the measurement results of current, which is three times than the simulation results. The six stages LNA exhibits 21.6 dB gain, 3 dB BW from 87 to 100.6 GHz, a minimum noise of 7 dB at 87 and 97 GHz, and a GBP of 163.5 GHz. The chip size of the six stages LNA is 0.56 mm2.
In chapter 3, a ka-band binary combine power using WIN 0.15 μm InGaAs procss is presented. The first stage series a RC in parallel to improce stability. The second stage combines 4 FETs by binary combine. The interdigitated capacitor is used in output matching to prevent the capacitance varation by its small capacitance. The stability check schematics are summarized, including stability K, inter stage stability, and non-linear stability. The PA exhibits 13.9 dB gain, the output power at 1 dB gain compression point is 17.7 dBm, and 24-dBm saturation output power. The chip size of the PA is 4.6 mm2.
Analysis, design and measured results for cascode PA in chapter 4. The gate bypass capacitor of common gate FET is introduced. Comparison of two types cascode PA layout is presented. The first cascode PA exhibits 4.5 dB gain, the output power at 1 dB gain compression point is 18 dBm, and 765 mW power comsumption. The second cascode PA exhibits 5.2 dB gain, the output power at 1 dB gain compression point is 19.3 dBm, and 740 mW power comsumption.

關鍵字(中)

★ 低雜訊放大器
★ 功率放大器
★ 毫米波
★ 微波

關鍵字(英)

論文目次

摘要 I
Abstract III
目錄 V
圖目錄 VII
表目錄 XII
第1章緒論 1
1.1 研究動機及背景 1
1.2 現況研究及發展 1
1.3 論文貢獻 2
1.4 論文架構 2
第2章 W頻段低雜訊放大器 3
2.1 簡介 3
2.2 TSMC 40 nm製程簡介 4
2.3 三級疊接低雜訊放大器 5
2.3.1 電路設計 5
2.3.2 電路量測結果 13
2.3.3 分析結果與討論 19
2.4 六級共源極低雜訊放大器 20
2.4.1 電路設計 20
2.4.2 電路量測結果 26
2.4.3 分析結果與討論 34
2.5 總結 34
第3章 Ka頻段功率放大器 36
3.1 簡介 36
3.2 WIN 0.15 μm InGaAs製程介紹 37
3.3 功率放大器設計 37
3.4 穩定度模擬 46
3.5 功率放大器量測結果 52
3.6 總結 59
第4章 Ka頻段功率放大器疊接佈局方式之比較 63
4.1 簡介 63
4.2 WIN 0.1 μm GaAs製程介紹 63
4.3 疊接架構設計分析[35]-[37] 63
4.4 疊接一功率放大器設計與量測 65
4.4.1 疊接一功率放大器設計 65
4.4.2 疊接一功率放大器量測結果 74
4.5 疊接二功率放大器設計與量測 80
4.5.1 疊接二功率放大器設計 80
4.5.2 疊接二功率放大器量測結果 84
4.6 總結 88
第5章結論 90
參考文獻 92

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指導教授

張鴻埜

審核日期

2018-7-19

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