憶阻式內容循址記憶體之測試

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：109

、訪客IP：3.149.238.239

姓名

鄧力瑋(Li-Wei Deng) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

憶阻式內容循址記憶體之測試
(Testing of Memristor-Based Content Addressable Memories)

相關論文

★ 應用於三元內容定址記憶體之低功率設計與測試技術	★ 用於隨機存取記憶體的接線驗證演算法
★ 用於降低系統晶片內測試資料之基礎矽智產	★ 內容定址記憶體之鄰近區域樣型敏感瑕疵測試演算法
★ 內嵌式記憶體中位址及資料匯流排之串音瑕疵測試	★ 用於系統晶片中單埠與多埠記憶體之自我修復技術
★ 用於修復嵌入式記憶體之基礎矽智產	★ 自我修復記憶體之備份分析評估與驗證平台
★ 使用雙倍疊乘累加命中線之低功率三元內容定址記憶體設計	★ 可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計
★ 低功率與可自我修復之三元內容定址記憶體設計	★ 多核心系統晶片之診斷方法
★ 應用於網路晶片上隨機存取記憶體測試及修復之基礎矽智產	★ 應用於貪睡靜態記憶體之有效診斷與修復技術
★ 應用於內嵌式記憶體之高效率診斷性資料壓縮與可測性方案	★ 應用於隨機存取記憶體之有效良率及可靠度提升技術

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

內容循址記憶體 (Content-Addressable Memory, CAM) 為一種被廣泛運用在
網絡系統中的元件。為了解決與功耗和面積的問題，許多非揮發性的內容循址記
憶體因此被提出。在這些非揮發性的內容循址記憶體中，憶阻式的內容循址記憶
體是一個不錯的候選元件。但是，現存的憶阻式內容循址記憶體其細胞架構和半
導體式內容循址記憶體其細胞架構有很大的不同，而且，也因為憶阻器引發了一
些錯誤機制。因此，憶阻式內容循址記憶體需要有效的測試方法及其錯誤模型。
在此篇論文，我們透過加入各種不同的電子性缺陷，像是電阻性開路、電阻
性短路、電晶體開路、電晶體短路、電阻式橋接，來定義 5T-2R 憶阻式內容定
址記憶體。然後，我們提出了一種行軍式測試演算法 March-MCAM 來涵蓋我們
所定義的 5T2R 憶阻式內容循址記憶體之比對性錯誤模型。 March-MCAM 需
要 6N 的寫入指令及 (14N+2B) 的比對指令來涵蓋一個 NxB-bit 5T-2R 憶阻式
內容循址記憶體的比對性錯誤模型，在此 14N 代表的是兩個比對指令需要執行
7 次。但是，憶阻式內容循址記憶體有許多不同的細胞架構，若要人工手動去一
一測試，會需要相當多的時間。因此，在論文的第二個部分我們提出了一個內容
循址記憶體自動化測試的方法。最後，我們提出了內容循址記憶體的行軍式測試
產生之演算法自動化的方法。此方法運用了讀與搜尋偵測之等效 Read-Compare
Detection Equivalence (RCDE) 來減少產生時間。最後，分析結果顯示，產生所需
要的時間比沒用 RCDE 的方法快了 2 倍。

摘要(英)

Content addressable memory (CAM) is one widely used component in network systems.
Recently, memristor-based CAMs have been proposed to cope with the power and area issues
of conventional CMOS-based CAMs. Among them, memristor-based CAM is considered as a
good candidate. However, existing memristor-based CAM cell structures are much different
from conventional CMOS-based CAM structures. Also, the fabrication process of memristor
device may induce new failure mechanisms. Therefore, effective fault modeling and testing
techniques for memristor-based CAMs are imperative.
In this thesis, we define comparison faults for 5T-2R memristor-based ternary CAMs
(mrTCAMs) by injecting the electrical defects of resistive open, short, transistor stuck-on,
transistor stuck-open, and bridge. Then, a March-like test, March-MCAM, is proposed to
cover the comparison faults of 5T-2R mrTCAMs. The March-MCAM requires 6N Write
operations and (14N+2B) Compare operations to cover 100% comparison faults of an N×B-
bit 5T-2R mrTCAM array where 14N represents 2 compare operaitons are executed 7 times.
However, different cell structures were proposed to realize mrTCAMs. It is time-consuming
to manually do the fault modeling and test algorithm design. Therefore, we also propose an
automation method for the fault modeling of CAMs. Finally, we propose a test algorithm
generation method for CAMs. The proposed method uses the Read-Compare Detection
Equivalence (RCDE) concept to reduce the test generation time. Analysis results show that
the proposed method can achieve about 2 times of generation time reduction in comparison
with the method without using RCDE concept.

關鍵字(中)

★ 憶阻器
★ 內容循址記憶體

關鍵字(英)

★ Memristor
★ CAM
★ TCAM
★ Fault model

論文目次

1 Introduction 1
1.1 Memristor . 1
1.2 Memristor-based CAMs . 2
1.2.1 CAMs . 2
1.2.2 Nonvolatile CAMs 3
1.3 Testing of CMOS-based CAMs and Memristor Memories . 4
1.4 Thesis Organization 5
2 Fault Modeling and Testing of Memristor-based TCAMs 6
2.1 Motivation . 6
2.2 NMOS-access mrTCAM Cell . 6
2.3 Electrical Fault Models of mrTCAM 8
2.3.1 Traditional Faults . 9
2.4 Test Algorithm for mrTCAMs 20
2.5 Relationship Between Defect and Defect Size 23
2.6 Summary . 24
3 Fault Modeling Automation for CAMs 25
3.1 Motivation . 25
3.2 Proposed Automatic Fault Modeling Method 25
3.2.1 Platform of Automatic Fault Modeling . 25
3.2.2 Flow of Automatic Fault Modeling . 26
3.2.3 Defect Simulation Flow 29
3.2.4 Classification . 29
3.3 Simulation Result . 32
3.3.1 Case Study 33
3.3.2 Analysis on Different Cell Structures 38
3.4 Summary . 43
4 Automatic Test Algorithm Generation for CAMs 44
4.1 Motivation . 44
4.2 Test Algorithm Generation by Simulation (TAGS) . 44
4.3 Algorithm Generation Strategy . 45
4.3.1 BCAM-Flow 46
4.3.2 TCAM-Flow 48
4.4 C-TAG Structure . 50
4.5 CAM Test Algorithm Generation 52
4.5.1 C-TAG Fault Simulator . 52
4.5.2 C-TAG Flow . 61
4.6 Simulation Result . 68
4.7 Summary . 72
5 Conclusion and Future Work 76
5.1 Conclusion . 76
5.2 Future Work 77

參考文獻

1] M. Mao, Y. Cao, S. Yu, and C. Chakrabarti, “Optimizing latency, energy, and relia-
bility of 1T1R ReRAM through appropriate voltage settings,” in IEEE Int’l Conf. on
Computer Design (ICCD), Oct 2015, pp. 359–366.
[2] L. Chua, “Memristor-The missing circuit element,” IEEE Trans. Circuit Theory, vol. 18,
no. 5, pp. 507–519, September 1971.
[3] S. Matsunaga, S. Miura, H. Honjou, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, and
T. Hanyu, “A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-
in-memory architecture,” in VLSI Circuits (VLSIC), IEEE Symposium, June 2012, pp.
44–45.
[4] M. F. Chang, L. Y. Huang, W. Z. Lin, Y. N. Chiang, C. C. Kuo, C. H. Chuang, K. H.
Yang, H. J. Tsai, T. F. Chen, and S. S. Sheu, “A ReRAM-Based 4T2R nonvolatile
TCAM using RC-filtered stress-decoupled scheme for frequent-off instant-on search en-
gines used in IoT and big-data processing,” IEEE Jour. of Solid-State Circuits, vol. 51,
no. 11, pp. 2786–2798, Nov 2016.
[5] S. Matsunaga, M. Natsui, S. Ikeda, K. Miura, T. Endoh, H. Ohno, and T. Hanyu,
“Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile
TCAM based on a reversed current reading scheme,” in Proc. Asia and South Pacific
Design Automation Conf. (ASP-DAC), Jan 2012, pp. 475–476.
[6] M. F. Chang, C. H. Chuang, Y. N. Chiang, S. S. Sheu, C. C. Kuo, H. Y. Cheng,
J. Sampson, and M. J. Irwin, “Designs of emerging memory based non-volatile TCAM
78
for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell,” in Proc.
IEEE Int’l Symp. on Circuits and Systems (ISCAS), May 2016, pp. 1142–1145.
[7] J. Li, R. K. Montoye, M. Ishii, and L. Chang, “1 Mb 0.41 2T-2R cell nonvolatile TCAM
with two-bit encoding and clocked self-referenced sensing,” IEEE Jour. of Solid-State
Circuits, vol. 49, no. 4, pp. 896–907, April 2014.
[8] K. Eshraghian, K. R. Cho, O. Kavehei, S. K. Kang, D. Abbott, and S. M. S. Kang,
“Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Fu-
ture High Performance Search Engines,” IEEE Trans. on Very Large Scale Integration
(VLSI) Systems, vol. 19, no. 8, pp. 1407–1417, Aug 2011.
[9] K.-J. Lin and C.-W. Wu, “Testing content-addressable memories using functional fault
models and march-like algorithms,” IEEE Trans. on Computer-Aided Design of Inte-
grated Circuits and Systems, vol. 19, no. 5, pp. 577–588, May 2000.
[10] R. S. Williams, “How we found the missing memristor,” IEEE Spectr., vol. 45, no. 12,
pp. 28–35, Dec 2008.
[11] D. B Strukov, G. S Snider, D. Stewart, and S. Williams, “The Missing Memristor
Found,” Nature, vol. 453, pp. 80–3, Jun 2008.
[12] E. Norige, A. X. Liu, and E. Torng, “A ternary unification framework for optimizing
TCAM-based packet classification systems,” in Proc. ACM/IEEE Archit. Netw. Com-
mun. Syst. (ANCS), Oct 2013, pp. 95–104.
[13] I. Syafalni and T. Sasao, “A TCAM generator for packet classification,” in IEEE Int’l
Conf. on Computer Design (ICCD), Oct 2013, pp. 322–328.
[14] C. R. Meiners, A. X. Liu, and E. Torng, “Topological transformation approaches to
TCAM-based packet classification,” IEEE/ACM Trans. Netw., vol. 19, no. 1, pp. 237–
250, Feb 2011.
79
[15] O. Rottenstreich, I. Keslassy, A. Hassidim, H. Kaplan, and E. Porat, “On finding an
optimal TCAM encoding scheme for packet classification,” in Proc. IEEE INFOCOM,
April 2013, pp. 2049–2057.
[16] Y. J. Chang, K. L. Tsai, and H. J. Tsai, “Low leakage TCAM for IP lookup using
two-side self-gating,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 6, pp.
1478–1486, June 2013.
[17] Y. Sun, H. Liu, and M. S. Kim, “Using TCAM efficiently for IP route lookup,” in Proc.
IEEE Consum. Commun. Netw. Conf. (CCNC), Jan 2011, pp. 816–817.
[18] H. Yu, “A memory- and time-efficient on-chip TCAM minimizer for IP lookup,” in Proc.
Conf. Design, Automation, and Test in Europe (DATE), March 2010, pp. 926–931.
[19] H. Yu, J. Chen, J. Wang, S. Q. Zheng, and M. Nourani, “An improved TCAM-based
IP lookup engine,” in Proc. Int. Conf. High Perform. Switch. Routing, May 2008, pp.
1–5.
[20] K. Mathan and T. Ravichandran, “Refined search enable (RSE) TCAM design used in
network routing table,” in Proc. Int. Conf. Pattern Recognit., Informat. Mobile Eng.
(PRIME), Feb 2013, pp. 412–417.
[21] Y. J. Chang, “Don’t-Care Gating (DCG) TCAM design used in network routing table,”
IEEE Trans. VLSI Systems, vol. 18, no. 11, pp. 1599–1607, Nov 2010.
[22] D. Lin and M. Hamdi, “Compress the route table stored in TCAM by using memory
filter,” in Proc. Int. Conf. High Perform. Switch. Routing, June 2009, pp. 1–6.
[23] T. Mishra and S. Sahni, “DUOS - Simple dual TCAM architecture for routing tables
with incremental update,” in Proc. IEEE Symp. Comput. Commun. (ISCC), June 2010,
pp. 503–508.
[24] M. F. Chang, C. C. Lin, A. Lee, Y. N. Chiang, C. C. Kuo, G. H. Yang, H. J. Tsai, T. F.
Chen, and S. S. Sheu, “A 3T1R nonvolatile TCAM using MLC ReRAM for frequent-off
80
instant-on filters in IoT and big-data processing,” IEEE Jour. of Solid-State Circuits,
vol. PP, no. 99, pp. 1–16, 2017.
[25] C. C. Lin, J. Y. Hung, W. Z. Lin, C. P. Lo, Y. N. Chiang, H. J. Tsai, G. H. Yang, Y. C.
King, C. J. Lin, T. F. Chen, and M. F. Chang, “A 256b-wordlength ReRAM-based
TCAM with 1ns search-time and 14X improvement in wordlength-energyefficiency-
density product using 2.5T1R cell,” in Proc. IEEE Int’l Solid-State Cir. Conf. (ISSCC),
Jan 2016, pp. 136–137.
[26] L. Zheng, S. Shin, S. Lloyd, M. Gokhale, K. Kim, and S. M. Kang, “RRAM-based
TCAMs for pattern search,” in Proc. IEEE Int’l Symp. on Circuits and Systems (IS-
CAS), May 2016, pp. 1382–1385.
[27] Y. Yang, J. Mathew, M. Ottavi, S. Pontarelli, and D. K. Pradhan, “2T2M memristor
based TCAM cell for low power applications,” in Proc. IEEE Int. Conf. Design Technol.
Integr. Syst. Nanoscale Era, April 2015, pp. 1–6.
[28] P. Junsangsri, F. Lombardi, and J. Han, “A memristor-based TCAM (Ternary Con-
tent Addressable Memory) cell,” in Proc. IEEE/ACM Int. Symp. Nanosc. Archit.
(NANOARCH), July 2014, pp. 1–6.
[29] S. Tabassum, F. Parveen, and A. B. M. H. u. Rashid, “Low power high speed ternary
content addressable memory design using 8 MOSFETs and 4 memristors - hybrid struc-
ture,” in Proc. Int. Conf. Elect. Comput. Eng. (ICECE), Dec 2014, pp. 168–171.
[30] J. F. Li, “Testing comparison faults of ternary content addressable memories with asym-
metric cells,” in IEEE Asian Test Symp. (ATS), Oct 2007, pp. 501–506.
[31] J.-F. Li, “Testing comparison faults of ternary CAMs based on comparison faults of
binary CAMs,” in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC),
vol. 1, Jan 2005, pp. 65–70 Vol. 1.
81
[32] ——, “Testing ternary content addressable memories with comparison faults using
march-like tests,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and
Systems, vol. 26, no. 5, pp. 919–931, May 2007.
[33] P. R. Sidorowicz and J. A. Brzozowski, “An approach to modeling and testing memories
and its application to CAMs,” in Proc. IEEE VLSI Test Symp. (VTS), April 1998, pp.
411–416.
[34] ——, “Verification of CAM tests for input stuck-at faults,” in Proc. IEEE Int’l Work-
shop on Memory Technology, Design and Testing (MTDT), Aug 1998, pp. 76–82.
[35] D. K. Bhaysar, “A built-in self-test method for write-only content addressable memo-
ries,” in Proc. IEEE VLSI Test Symp. (VTS), May 2005, pp. 9–14.
[36] N. Z. Haron and S. Hamdioui, “On Defect Oriented Testing for Hybrid
CMOS/Memristor Memory,” in 2011 Asian Test Symposium, Nov 2011, pp. 353–358.
[37] S. Kannan, J. Rajendran, R. Karri, and O. Sinanoglu, “Sneak-path Testing of
Memristor-based Memories,” in 2013 26th International Conference on VLSI Design
and 2013 12th International Conference on Embedded Systems, Jan 2013, pp. 386–391.
[38] S. Kannan, N. Karimi, R. Karri, and O. Sinanoglu, “Modeling, Detection, and Diag-
nosis of Faults in Multilevel Memristor Memories,” Proc. IEEE/ACM Int’l Conf. on
Computer-Aided Design (ICCAD), vol. 34, no. 5, pp. 822–834, May 2015.
[39] T. Y. Lin, Y. X. Chen, J. F. Li, C. Y. Lo, D. M. Kwai, and Y. F. Chou, “A Test Method
for Finding Boundary Currents of 1T1R Memristor Memories,” in Proc. IEEE Asian
Test Symp. (ATS), Nov 2016, pp. 281–286.
[40] Y. Luo, X. Cui, M. Luo, and Q. Lin, “A high fault coverage march test for 1T1R
memristor array,” in Int’l Conf. on Electron Devices and Solid-State Circuits (EDSSC),
Oct 2017, pp. 1–2.
[41] Y. X. Chen and J. F. Li, “Fault modeling and testing of 1T1R memristor memories,”
in Proc. IEEE VLSI Test Symp. (VTS), April 2015, pp. 1–6.
82
[42] P. Liu, Z. You, J. Kuang, Z. Hu, H. Duan, andW.Wang, “Efficient March test algorithm
for 1T1R cross-bar with complete fault coverage,” Electronics Letters, vol. 52, no. 18,
pp. 1520–1522, 2016.
[43] M. Escudero-Lopez, F. Moll, A. Rubio, and I. Vourkas, “An on-line test strategy and
analysis for a 1T1R crossbar memory,” in IEEE Int’l Symp. on On-Line Testing and
Robust System Design (IOLTS), July 2017, pp. 120–125.
[44] D. Biolek, Z. Biolek, and V. Biolkova, “SPICE modeling of memristive, memcapacitative
and meminductive systems,” in Proc. Eur. Conf. Circuit Theory Design (ECCTD), Aug
2009, pp. 249–252.
[45] J.-F. Li and C.-K. Lin, “Modeling and testing comparison faults for ternary content
addressable memories,” in Proc. IEEE VLSI Test Symp. (VTS), May 2005, pp. 60–65.
[46] C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, “Simulation-based test algorithm
generation for random access memories,” in Proc. IEEE VLSI Test Symp. (VTS), 2000,
pp. 291–296.
[47] C.-F. Wuss, C.-T. Huang, and C.-W. Wu, “RAMSES: a fast memory fault simulator,”

指導教授

李進福(Jin-Fu Li)

審核日期

2018-8-21

推文