基於雅可比疊代法之軟性輸出的 巨量多輸入多輸出偵測器設計

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徐常軒(Chang-Hsuan Hsu) 查詢紙本館藏

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電機工程學系

論文名稱

基於雅可比疊代法之軟性輸出的巨量多輸入多輸出偵測器設計
(A Design of Soft-output Massive MIMO Detector Based on Jacobi Iterative Method)

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摘要(中)

在巨量多輸入多輸出系統中，最小均方誤差(MMSE)演算法在上行信號偵測扮演著非常重要的角色因為它能夠使效能逼近最佳解並且降低複雜度(線性)。然而，演算法中的反矩陣運算複雜度會隨著使用者的增加而變得很大，硬體實現上也變得很困難。本論文提出了一個降低運算複雜度和節省硬體資源，且可平行運算的管線式架構的最小均誤差偵測器，並且加入了通道編碼和解碼器，產生軟性解調輸出來增加位元錯誤率之效能。一開始，前處理單元(PU)會先計算演算法中的格拉姆矩陣的值(Gram matrix)和匹配濾波器(Matched Filter)的輸出值，文獻中，會使用下三角(或上三角)的脈動陣列(Systolic array)來計算，利用此法的好處是運算完的格拉姆矩陣的值不需要存起來，直接灌到下一級使用，但是需要非常多的處理元件來做運算。此外，因為格拉姆矩陣為對稱矩陣，因此矩陣的右下角(或左上角)的值是不需要計算的，這樣非常浪費運算資源。本論文根據矩陣的對稱性，使需要計算的格拉姆值達到最低，大大地節省了硬體資源。接著會進入第二級來進行解碼，使用的是雅可比疊代(Jacobi iteration)，因其能夠平行處理而不需要相繼處理訊號。最後再計算軟性輸出值。硬體實現上先利用 SMIMS VeriEnterprise Xilinx FPGA進行即時驗證電路功能，接著晶片實現上利用 90 nm 製成來設計晶片，晶片的核心面積為 3.34 mm^2，最高操作頻率為 327 MHZ 且動態功率消耗為 47.3 mW 。

摘要(英)

The minimum-mean-square-error (MMSE) plays a significant role in the massive multiple-input-multiple-output (MIMO) system uplink signal detection. However, matrix inversion computing complexity of the MMSE algorithm increases largely when the number of users is high, and hardware implementation is difficult. This thesis proposes a reducing complexity, frugal hardware resource, parallel processing and pipelining architecture MMSE detector. The channel encoder and decoder are used to improve bit error rate by soft output value. Firstly, Preprocessing units (PU) are used to calculate Gram matrix and Matched Filter output of the algorithm. In the literature, the lower-triangular (or upper-triangular) systolic array are proposed, the benefit of this architecture is that the value of the Gram matrix don’t need to store and then output to next stage directly, but needs more processing element for computing. In addition, since gram matrix is symmetric, the value of the Gram matrix bottom right corner (or upper left corner) don’t need to be calculated, and then the computing complexity can be reduced. According to symmetric of the matrix, this thesis reduces the computation of gram matrix value which only need to compute lowest. Hence, we can save hardware resource highly. Secondly, Jacobi iteration is used to decode in the second stage because it could process in parallel instead of sequential processing signal to calculate the soft output value. Finally, this design is verified on SMIMS VeriEnterprise Xilinx FPGA, and the proposed design is implemented in 90 nm CMOS technology. The core area is 3.34 mm^2, maximum clock frequency is 327 MHz, and dynamic power consumption is 47.3 mW.

關鍵字(中)

★ 巨量多輸入多輸出系統
★ 最小均方誤差
★ 軟性輸出
★ 雅可比疊代

關鍵字(英)

★ Massive MIMO
★ MMSE
★ soft-output
★ Jacobi iteration

論文目次

目錄
摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vii
表目錄 ix
第一章緒論 1
1.1 背景 1
1.2 研究動機 2
1.3 論文架構 4
第二章巨量多輸入多輸出系統介紹 5
2.1 點對點多輸入多輸出系統 5
2.2 多用戶多輸入多輸出系統 6
2.3 巨量多輸入多輸出系統 8
2.4 通道容量 9
2.5 空間多工技術 10
2.6 空間多工線性偵測演算法 11
2.6.1 最大比率合成(Maximum Ratio Combining) 11
2.6.2 強制歸零(Zero Forcing) 12
2.6.3 最小均方誤差(Minimum Mean Square Error) 12
2.7 空間多工非線性偵測演算法 13
2.7.1 最大相似偵測法(Maximum Likelihood) 13
2.7.2 樹狀搜尋 14
2.8 偵測器解調輸出 17
2.8.1 硬性解調輸出 17
2.8.2 軟性解調輸出 18
2.8.3 比較未編碼、硬性解調與軟性解調輸出差異 19
第三章軟性解調巨量多輸入多輸出偵測器 23
3.1 系統架構 24
3.2 Cholesky 分解與 LDL 分解 24
3.3 近似反矩陣演算法 26
3.3.1 諾伊曼級數估計(Neumann series approximation) 26
3.3.2 定常疊代法(Stationary Iterative Method) 28
3.4 高效率硬體前處理與近似反矩陣疊代演算法 32
3.5 軟性解調輸出值產生器的簡化 37
3.6 複雜度與效能分析 40
第四章硬體架構設計 42
4.1 硬體設計規格 42
4.2 基本電路介紹 44
4.2.1 前處理電路(Preprocessing Circuit) 44
4.2.2 倒數電路(Reciprocal Circuit) 46
4.2.3 信號干擾雜訊比運算電路(SINR Circuit) 50
4.2.4 雅可比疊代(Jacobi iteration)偵測電路 51
4.2.5 軟性輸出值產生器(Soft Value Generator) 52
4.2.6 有限狀態機(FSM) 53
第五章晶片實現 55
5.1 設計流程 55
5.2 定點數模擬分析 56
5.3 模擬驗證 57
5.4 其他文獻比較 59
第六章結論與未來展望 60
參考文獻 61

參考文獻

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指導教授

薛木添(Muh-Tian Shiue)

審核日期

2018-10-8

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