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姓名	廖柏翔(Po-Hsiang Liao)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	鍺奈米球/二氧化矽/矽鍺殼異質結構之應力工程與無接面N型金氧半場效電晶體研製 (Strain engineering on Ge-nanosphere/SiO2/Si1-xGex-shell heterostructure and junctionless n-MOSFETs)
相關論文	★ 量身訂作鍺量子點崁入式發射器與鍺量子點光偵測器應用於單石積體化矽光電晶片
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摘要(中)	為了提高電晶體的特性以增進人類福祉，更換電晶體之通道材料已經勢在必行。在所有可能的材料中鍺因為具有較矽通道更高的電子電洞遷移率而備受矚目，更重要的是鍺材料與現今互補式金屬氧化物半導體製程相容。然而要實現鍺金氧半元件之難度在於將低缺陷密度之高品質鍺沉積在矽上，以及在鍺材料上形成令人滿意的界面與電特性之閘介電層，此兩種對鍺元件來說相當具有挑戰性。此外，摻雜活化效率低、摻雜擴散快以及費米能接釘住之問題，更讓N型鍺通道電晶體較P型鍺通道電晶體更難實現。我們研究團隊過去已利用單一步驟氧化的方式，成功在矽基板上製作出獨特的自聚式鍺奈米球/二氧化矽/矽鍺奈米片異質結構。基於這樣的結構，本文提出局部高濃度矽鍺奈米片之結構，以達到高性能矽鍺甚至是純鍺之N型金氧半場效電晶體之應用。 　　為了製作鍺奈米球/二氧化矽/矽鍺奈米片金氧半場效電晶體，本文討論了矽鍺柱氧化完後之二氧化矽與鍺奈米球/二氧化矽/矽鍺奈米片之幾何結構尺寸調控。尺寸調控0.75%–3.2%的伸張式應力與0.7%–4.5%的壓縮式應力，已分別在鍺奈米晶粒包覆在二氧化矽與氮化矽的結構中得到驗證。在伸張式或壓縮式應力下，鍺量子點之晶格畸變也藉由量測格留乃森参数、非和諧參數與選區繞射圖得到驗證。介入氧化層厚度2.5奈米至4.5奈米與矽鍺奈米片厚度2.3奈米至22.5奈米，已藉由鍺奈米球鑽入矽基板之厚度所調控。此外，矽鍺片之晶格方向似乎沿襲著一開始矽基板晶格方向來成長。鍺濃度為85%、壓縮式應力為3%之單晶(100)矽鍺通道也成功地被驗證。另外，鍺濃度為35%、壓縮式應力為1.5%之單晶(110)矽鍺通道也成可成功地被製作出來。 　　結合以上的技術，本文已利用自聚式鍺奈米球/二氧化矽/矽鍺奈米片異質結構，成功地在(100)面絕緣體上的矽層中，製造並量測出鍺含量為85%之矽鍺無界面N型電晶體。我們的鍺奈米球/二氧化矽/矽鍺奈米片閘堆疊結構，在閘介電層沉積之前或之後，無須進行表面處理後額外的回火。在通道長度為75奈米，溫度為80K下給定閘極偏壓+1V、汲極偏壓+1V，量測到次臨限斜率為150mV/dec與開關路電流比大於5×108，顯示此元件具有優越的閘控制能力。計算所得之載子遷移率高達312.84cm2/V·s。最後，本文中也討論了源/汲極電阻、外在與固有之轉導、及轉導效率等進一步的元件特性。
摘要(英)	To boost the performance of the transistor for improving the human’s life, change the channel material is imperative definitely. Among the possible materials for the replacement of the Si channel, Ge is particularly attractive due to the high mobility for both electrons and holes. Most importantly Ge is compatible with the current CMOS technology. However, the challenge for the realization of the Ge MOS devices lies in the growth of high-quality Ge on Si with sufficiently low defect densities as well as the formation of gate dielectric on Ge with satisfactory interfacial and electrical properties, both of which are incredibly challenging. Furthermore, the low dopant activation efficiency, high dopant diffusivity, and the Fermi-level pinning lead to the realization for the Ge n-MOSFET is much more difficult than Ge p-MOSFET. Our group had successfully demonstrated unique self-assembly, gate-stack heterostructure of Ge nanosphere/SiO2/Si1-xGex nanosheet on the top of Si substrate using a one-step oxidation process. Base on this result, this thesis purpose a local, high Ge contents Si1-xGex nanosheet structure to achieve the high-performance Si1-xGex n-MOSFET. 　　In order to fabricate the Ge nanosphere/SiO2/Si1-xGex nanosheet MOSFET, this thesis has discussed the geometrical size control for the growing oxide formed by Si1-yGey nano-pillar oxidation, and the tunability for the heterostructure of Ge nanosphere/SiO2/Si1-xGex. Size-tunable strain engineering for the tensile strains of 0.75%–3.2% and compressive strain of 0.7%–4.5% have been demonstrated for the Ge nanocrystals embedded within the SiO2 and Si3N4 respectively. The crystalline distortions are observed in both strain states as evidenced by measurements of the Grüneisen parameters, anharmonic parameters, and lattice spacings through the selective area diffraction patterns. The intervening SiO2 thickness of 2.5nm–4.5nm and Si1-xGex nanosheet thickness of 2.3nm–22.5nm are successfully tailored by the penetration depth of the Ge nanosphere within the Si substrate. Furthermore, the crystalline orientation of the Si1-xGex nanosheet appears to inherit the original crystal orientation of these Si layers. Single-crystalline (100) Si1-xGex channels with Ge content as high as x = 0.85 and a compressive strain of 3% were successfully demonstrated. Additionally, (110) Si1-xGex channels with Ge content as high as x = 0.35 with a corresponding compressive strain of 1.5% were shown to be feasible. 　　Armed with these techniques, this thesis has successfully fabricated and characterized the Si0.15Ge0.85 junctionless n-MOSFETs comprising a gate-stacking heterostructure of Ge-nanospherical gate/SiO2/Si0.15Ge0.85-nanosheet on SOI (100) substrate in a self-organization approach. No surface treatments before the gate-dielectrics deposition nor additional processes following gate-stack formation are needed for our Ge nanosphere/SiO2/Si1-xGex nanosheet gate-stacking structure. Superior gate modulation is evidenced by subthreshold slope of 150mV/dec and ION/IOFF > 5×108 (IOFF < 10-6 uA/um and ION > 500 uA/um) measured at VG = +1V, VD = +1V, and T = 80K for our device with channel length of 75nm. The calculated mobility reaches as high as 312.84 cm2/V·s. Device detail properties such as S/D resistance, extrinsic and intrinsic transconductance, as well as transconductance efficiency are also discussed in this thesis.
關鍵字(中)	★ 應力工程 ★ 鍺閘極 ★ 矽鍺奈米薄層 ★ 無接面場效電晶體 ★ 自聚	關鍵字(英)	★ Strain engineering ★ Ge gate ★ SiGe nanosheet ★ junctionless FET ★ self organization
論文目次	摘要 i Abstract iii 誌謝 v Table of contents viii List of figures xi List of tables xxiv Chapter 1 Introduction 1 1-1 Development of the transistor and IC 1 1-2 Possible solution for MOSFET scaling 2 1-2-1 Sub-thermionic transition and new device configurations 3 1-2-2 Alternative channel materials to improve the device performance 5 1-3 Challenges for Ge channel MOSFET 6 1-3-1 Heteroepitaxy of Ge on Si 6 1-3-2 Suitable gate dielectric for Ge channel devices 8 1-3-3 Development status for the Ge n- and p-MOSFET 10 1-4 Heterostructure of Ge nanosphere/SiO2/Si1-xGex nanosheet: New solution for the Ge MOSFET 11 1-5 Dissertation organization 15 Chapter 1 Reference 22 Chapter 2 Formation of self-organized Ge nanospherical gate/SiO2/SiGe shell-shaped nanosheet on Si substrate 31 2-1 Formation mechanism for the heterostructure of Ge NP/SiO2/Si1-xGex 32 2-2 Expansion for the growing SiO2 after Si1-yGey nano-pillar oxidation 34 2-3 Sample clean issues for the Ge substrate and growing oxide 37 2-3-1 Sample clean on Ge substrate 37 2-3-2 Sample clean on growing oxide 38 2-3-3 Conclusion in this section 39 Chapter 2 Reference 47 Chapter 3 Matrix strain engineering in Ge nanocrystals by embedding within SiO2 and Si3N4 49 3-1 Introduction for the Raman measurement 49 3-1-1 Principle for the Raman measurement 50 3-1-2 Raman phonon line shift and the meaning of Raman linewidth 51 3-2 Strain engineering for the Ge nanocrystals embedded within the SiO2. 54 3-3 Strain engineering for the Ge nanosphere embedded in Si3N4 56 3-4 Distortions of the diamond cubic lattice for the Ge NPs/NCs 58 3-5 Release for the compressive-strained Ge nanosphere 60 3-6 Strain engineering for the Ge NPs burrowing into the SOI substrate 61 3-7 Chapter summary 62 Chapter 3 Reference 70 Chapter 4 Gate-stack engineering and Si1-xGex channel properties for Ge MOS devices 75 4-1 Silicon interstitials effects to the Ge NP 75 4-2 Controllability for the depth of penetration of the Ge NP 77 4-3 The controllability for the thickness of intervening SiO2 layer 78 4-4 The thickness and properties for the single crystalline Si1-xGex shell 80 4-4-1 The thickness control for the single crystalline Si1-xGex shell 80 4-4-2 Crystal orientation for the Si1-xGex shell 81 4-4-3 Chemical composition and strain for the Si1-xGex shell 82 4-4-4 Crystallinity quality for the Si1-xGex shell 85 4-5 Chapter summary 86 Chapter 4 Reference 95 Chapter 5 Fabrication for self-organized Ge nanosphere/SiO2/Si1-xGex junctionless nMOSFET 97 5-1 Introduction 97 5-2 Si1-xGex JL nFET fabrication process flow and key process development 98 5-2-1 Development for the E-beam alignment 98 5-2-2 SF6 lateral etching test 101 5-3 Fabrication for the Si1-xGex JL nMOSFET 102 5-3-1 Film stacks and zero mask patterning 103 5-3-2 Si0.85Ge0.15 nano-pillar patterning and oxidation 104 5-3-3 Active area definition and implantation 106 5-3-4 Channel passivation and gate contact patterning 107 5-3-5 In situ n+ poly Si deposition, dopant annealing and gate patterning 109 5-3-6 Standard backend process 110 5-4 Process optimization and simplification 111 5-4-1 Process optimization 111 5-4-2 Process simplification 112 Chapter 5 Reference 126 Chapter 6 Electrical characteristics for the Si1-xGex junctionless MOSFET 127 6-1 Introduction 127 6-2 Electrical characteristics for the Si0.15Ge0.85 channel JL MOSFET 129 6-3 Resistance, gm efficiency, mobility, and optical property for the Si0.15Ge0.85 channel JL MOSFET 131 6-3-1 gm efficiency for the Si0.15Ge0.85 channel JL MOSFET 132 6-3-2 Resistance for the Si0.15Ge0.85 channel JL MOSFET 132 6-3-3 Intrinsic transconductance (gm,int) and effective mobility (mFE) 134 6-3-4 Optical property for the Si0.15Ge0.85 channel JL MOSFET 135 6-4 Peeling and disappear for the Ge NP gate after several times electrical stress 135 6-5 Chapter summary 135 Chapter 6 Reference 143 Chapter 7 Conclusion and future work 146 7-1 Conclusion 146 7-2 Future work 148 Chapter 7 Reference 153 Appendix A. Global alignment ability in ELS7500 at National Nano Device Laboratories (NDL) A
參考文獻	Chapter 1 reference [1] J. Bardeen and W. H. Brattain, “The transistor, a semi-conductor triode,” Phys. Rev., vol. 74, no. 2, pp. 230–231, Jul. 1948. [2] W. Shockley, “The theory of p‐n junctions in semiconductors and p‐n junction transistors,” Bell Syst. Tech. J., vol. 28, no. 3, pp. 435–489, Jul. 1949. [3] P. Siffert and E. F. Krimmel, Silicon: Evolution and Future of a Technology. Berlin: New York: Springer, 2004. [4] D. Kahng and M. M. Atalla, “Silicon-silicon dioxide surface device,” in IRE Device Research Conference, Pittsburgh, USA, 1960. (This paper can be found in S. M. Sze, Semiconductor Devices: Pioneering Papers, World Scientific, Singapore, 1991.) [5] S. M. Sze and M. K. Lee, Semiconductor devices: physics and technology 3rd, Hoboken, N. J.: Wiley, 2013. [6] F. Mayer et al., “Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible tunnel FET performance,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2008, pp. 163–167. [7] K. Gopalakrishnan, P. B. Griffin and J. D. Plummer, “I-MOS: A novel semiconductor device with a subthreshold slope lower than kT/q,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2002, pp. 289–292. [8] K. Gopalakrishnan, P. B. Griffin and J. D. Plummer, “Impact ionization MOS (I-MOS)-Part I: Device and circuit simulations,” IEEE Trans. Elec. Dev., vol. 52, no. 1, pp. 69–76, Jan. 2005. [9] K. Gopalakrishnan, R. Woo, C. Jungemann, P. B. Griffin, and J. D. Plummer, “Impact ionization MOS (I-MOS)-part II: Experimental results,” IEEE Trans. Elec. Dev., vol. 52, no. 1, pp. 77–84, Jan. 2005. [10] S. Salahuddin and S. Datta, “Use of negative capacitance to provide voltage amplification for low power nanoscale devices,” Nano Lett., vol. 8, no. 2, pp 405–410, Dec. 2008. [11] A. I. Khan, C. W. Yeung, C. Hu, and S. Salahuddin, “Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation,” in IEDM Tech. Dig., Washington, DC, USA, Dec. 2011, pp. 255–258. [12] B. Obradovic, T. Rakshit, R. Hatcher, J. A. Kittl, and M. S. Rodder, “Ferroelectric switching delay as cause of negative capacitance and the implications to NCFETs,” in VLSI Tech. Dig., Honolulu, HI, USA, Jun. 2018, pp. 51–52. [13] H. Mertens et al., “Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates,” in VLSI Tech. Dig., Honolulu, HI, USA, Jun. 2016, pp. 158–159. [14] N. Loubet et al., “Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET,” in VLSI Tech. Dig., Kyoto, Japan, Jun. 2017, pp. 230–231. [15] J. P. Colinge et al., “Nanowire transistors without junctions,” Nature Nanotech., vol. 5, no. 3, pp. 225–229, Mar. 2010. [16] C. W. Lee et al., “Junctionless multigate field-effect transistor,” Appl. Phys. Lett., vol. 94, no. 5, pp. 053511-1–053511-2, Feb. 2009. [17] A. Nazarov et al., Semiconductor-on-insulator materials for nanoelectronics applications. Berlin Heidelberg: Springer, 2011. [18] H. C. Lin, C. I Lin, and T. Y. Huang, “Characteristics of n-type junctionless poly-Si thin-film transistors with an ultrathin channel,” IEEE Elec. Dev. Lett., vol. 33, no. 1, pp. 53–55, Jan. 2012. [19] Y. Kamata, “High-k/Ge MOSFETs for future nanoelectronics,” Materials Today, vol. 11, no. 1-2, pp. 30–38, Jan.–Feb. 2008. [20] K. Saraswat, “How far can we push Si CMOS? What lies beyond?” 2010. Available: https://web.stanford.edu/class/ee311/NOTES/Future%20Devices.pdf [21] S. Takagi, “Re-examination of subband structure engineering in ultra-short channel MOSFETs under ballistic carrier transport,” in VLSI Tech. Dig., Kyoto, Japan, Jun. 2003, pp. 115–116. [22] F. M. Bufler, K. Miyaguchi, T. Chiarella, N. Horiguchi, and A. Mocuta, “On the ballistic ratio in 14nm-Node FinFETs,” in European Solid-State Device Research Conference (ESSDERC), Leuven, Belgium, Sep. 2017, pp. 176–179. [23] J. Wang and M. Lundstrom, “Does source-to-drain tunneling limit the ultimate scaling of MOSFETs?,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2002, pp. 707–710. [24] S. Koba et al., “Channel length scaling limits of III–V channel MOSFETs governed by source-drain direct tunneling,” Jpn. J. Appl. Phys., vol. 53, no. 4S, pp. 04EC10-1–04EC10-5, Feb. 2014. [25] P. S. Goley and M. K. Hudait, “Germanium based field-effect transistors: Challenges and opportunities,” Materials, vol. 7, no. 3, pp. 2301–2339, Mar. 2014. [26] Y. Kamata, Y. Kamimuta, T. Ino and A. Nishiyama, “Direct comparison of ZrO2 and HfO2 on Ge substrate in terms of the realization of ultrathin high-k gate stacks,” Jpn. J. Appl. Phys., vol. 44, no. 4B, pp. 2323–2329, Apr. 2005. [27] F. K. LeGoues, B. S. Meyerson, and J. F. Mora, “Anomalous strain relaxation in SiGe thin films and superlattices,” Phys. Rev. Lett., vol. 66, no. 22, pp. 2903–2906, Jun. 1991. [28] D. J. Eaglesham and M. Cerullo, “Dislocation-free Stranski-Krastanow growth of Ge on Si(100),” Phys. Rev. Lett., vol. 64, no. 16, pp. 1943–1946, Apr. 1990. [29] G. L. Luo et al., “High-speed GaAs metal gate semiconductor field effect transistor structure grown on a composite substrate,” J. Appl. Phys., vol. 101, no. 8, pp. 084501-1–084501-6, Apr. 2007. [30] R. Pillarisetty et al., “High mobility strained germanium quantum well field effect transistor as the P-channel device option for low power (Vcc = 0.5 V) III-V CMOS architecture,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2010, pp. 150–153. [31] M. T. Currie, S. B. Samavedam, T. A. Langdo, C. W. Leitz, and E. A. Fitzgerald, “Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing,” Appl. Phys. Lett., vol. 72, no. 14, pp. 1718–1720, Apr. 1998. [32] T. F. Wietler, E. Bugiel, and K. R. Hofmann, “Surfactant-mediated epitaxy of relaxed low-doped Ge films on Si(001) with low defect densities,” Appl. Phys. Lett., vol. 87, no. 18, pp. 182102-1–182102-3, Oct. 2005. [33] J. S. Park et al., “Low-defect-density Ge epitaxy on Si(001) using aspect ratio trapping and epitaxial lateral overgrowth,” Electrochem. Solid-State Lett., vol. 12, no. 4, pp. H142–H144, Jan. 2009 [34] J. Suh, R. Nakane, N. Taoka, M. Takenaka, and S. Takagi, “Highly strained-SiGe-on-insulator p-channel metal-oxide-semiconductor field-effective transistors fabricated by applying Ge condensation technique to strained-Si-oninsulator substrates,” Appl. Phys. Lett., vol. 99, no. 14, pp. 142108-1–142108-3, Oct. 2011. [35] J. W. Seo et al., “Epitaxial germanium-on-insulator grown on (001) Si,” Microelectron. Eng., vol. 84, no. 9–10, pp. 2328–2331, Sep. 2007. [36] M. K. Hudait et al., “Heterogeneous integration of enhancement mode In0.7Ga0.3As quantum well transistor on silicon substrate using thin (< 2 m) composite buffer architecture for high-speed and low-voltage (0.5V) logic applications,” in IEDM Tech. Dig., Washington, DC, USA, Dec. 2007, pp. 625–628. [37] A. Nayfeh, C. O. Chui, T. Yonehara, and K. C. Saraswat, “Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si,” IEEE Elec. Dev. Lett., vol. 26, no. 5, pp. 311–313, May 2005. [38] A. Nayfeh, C. O. Chui, K. C. Saraswat, and T. Yonehara, “Effects of hydrogen annealing on heteroepitaxial-Ge layers on Si: Surface roughness and electrical quality,” Appl. Phys. Lett., vol. 85, no. 14, pp. 2815–2817, Oct. 2004. [39] D. Choi, Y. Ge, J. S. Harris, J. Cagnon, and S. Stemmer, “Low surface roughness and threading dislocation density Ge growth on Si (001),” J. Cryst. Growth, vol. 310, no. 18, pp. 4273–4279, Aug. 2008. [40] J. M. Hartmann et al., “Reduced pressure-chemical vapor deposition of intrinsic and doped Ge layers on Si(001) for microelectronics and optoelectronics purposes,” J. Cryst. Grow, vol. 274, no. 1-2, pp. 90–99, Jan. 2005. [41] H. Y. Yu, J. H. Park, A. K. Okyay, and K. C. Saraswat, “Selective-area high-quality germanium growth for monolithic integrated optoelectronics,” IEEE Elec. Dev. Lett., vol. 33, no. 4, pp. 579–581, Apr. 2012. [42] T. H. Loh et al., “Ultrathin low temperature SiGe buffer for the growth of high quality Ge epilayer on Si(100) by ultrahigh vacuum chemical vapor deposition,” Appl. Phys. Lett., vol. 90 no. 9, pp. 092108-1–092108-3, Feb. 2007. [43] X. Ma et al., “Fabrication of high Ge content SiGe-on-insulator with low dislocation density by modified Ge condensation,” Appl. Surf. Sci., vol. 255, no. 17, pp. 7743–7748, May 2009. [44] F. K. LeGoues, M. Copel, and R. M. Tromp, “Microstructure and strain relief of Ge films grown layer by layer on Si(001),” Phys. Rev. B, vol. 42, no. 18, pp. 11690–11700, Dec. 1990. [45] D. Tetzlaff, T. F. Wietler, E. Bugiel, and H. J. Osten, “Carbon-mediated growth of thin, fully relaxed germanium films on silicon,” Appl. Phys. Lett., vol. 100, no. 1, 012108-1–012108-3, Jan. 2012. [46] J. S. Park et al., “Defect reduction of selective Ge epitaxy in trenches on Si(001) substrates using aspect ratio trapping,” Appl. Phys. Lett., vol. 90 no. 5, pp. 052113-1–052113-3, Feb. 2007. [47] H. K. Liou, P. Mei, U. Gennser, and E. S. Yang, “Effects of Ge concentration on SiGe oxidation behavior,” Appl. Phys. Lett., vol. 59, no. 10, pp. 1200–1202, Jun. 1991. [48] K. W. Jo, W. K. Kim, M. Takenaka, and S. Takagi, “Hole mobility enhancement in extremely-thin-body strained GOI and SGOI pMOSFETs by improved Ge condensation method,” in VLSI Tech. Dig., Honolulu, HI, USA, Jun. 2018, pp. 195–196. [49] M. M. Frank, “High-k/metal gate innovations enabling continued CMOS scaling,” in Proc. of the ESSCIRC, Helsinki, Finland, Sep. 2011, pp. 50–58. [50] K. Prabhakaran, F. Maeda, Y. Watanabe, and T. Ogino, “Distinctly different thermal decomposition pathways of ultrathin oxide layer on Ge and Si surfaces,” Appl. Phys. Lett., vol. 76, no. 16, pp. 2244–2246, Feb. 2000. [51] K. Kita et al., “Control of high-k/germanium interface properties through selection of high-k materials and suppression of GeO volatilization,” Appl. Surf. Sci., vol. 254, no. 19, pp. 6100–6105, Jul. 2008. [52] C. H. Lee et al., “Ge/GeO2 interface control with high-pressure oxidation for improving electrical characteristics,” Appl. Phys. Express, vol. 2, no. 7, pp. 071404-1–071404-3, Jul. 2009. [53] C. H. Lee, T. Nishimura, K. Nagashio, K. Kita, and A. Toriumi, “High-electron-mobility Ge/GeO2 n-MOSFETs with two-step oxidation,” IEEE Trans. Elec. Dev., vol. 58, no. 5, pp. 1295–1301, May 2011. [54] R. Zhang, T. Iwasaki, N. Taoka, M. Takenaka, and S. Takagi, “High-mobility Ge pMOSFET with 1-nm EOT Al2O3/GeOx/Ge gate stack fabricated by plasma post oxidation,” IEEE Trans. Elec. Dev., vol. 59, no. 2, pp. 335–341, Feb. 2012. [55] R. Zhang, N. Taoka, P. C. Huang, M. Takenaka, and S. Takagi, “1-nm-thick EOT high mobility Ge n- and p-MOSFETs with ultrathin GeOx/Ge MOS interfaces fabricated by plasma post oxidation,” in IEDM Tech. Dig., Washington, DC, USA, Dec. 2011, pp. 642–645. [56] S. H. Yi, K. S. Chang-Liao, T. Y. Wu, C. W. Hsu, and J. Huang, “High performance Ge pMOSFETs with HfO2/Hf-Cap/GeOx gate stack and suitable post metal annealing treatments,” IEEE Elec. Dev. Lett., vol. 38, no. 5, pp. 544–547, May 2017. [57] W. H. Chang, H. Ota, and T. Maeda, “Gate-first high-performance germanium nMOSFET and pMOSFET using low thermal budget ion implantation after germanidation technique,” IEEE Elec. Dev. Lett., vol. 37. No. 3, pp. 253–256, Mar. 2016. [58] T. Hosoi et al., “Schottky source/drain germanium-based metal-oxide-semiconductor field-effect transistors with self-aligned NiGe/Ge junction and aggressively scaled high-k gate stack,” Appl. Phys. Lett., vol. 107, no. 25, pp. 252104-1–252104-4, Dec. 2015. [59] M. Koike et al., “Diffusion and activation of n-type dopants in germanium,” J. Appl. Phys., vol. 104, no. 2, pp. 023523-1–023523-5, Jul. 2008. [60] A. Dimoulas, P. Tsipas, A. Sotiropoulos, and E. K. Evangelou, “Fermi-level pinning and charge neutrality level in germanium,” Appl. Phys. Lett., vol. 89, no. 25, pp. 252110-1–252110-3, Dec. 2006. [61] T. Nishimura, K. Kita, and A. Toriumi, “Evidence for strong Fermi-level pinning due to metal-induced gap states at metal/germanium interface,” Appl. Phys. Lett., vol. 91, no. 12, pp. 123123-1–123123-3, Sep. 2007. [62] J. Kim, S. W. Bedell, and D. K. Sadana, “Improved germanium n+/p junction diodes formed by coimplantation of antimony and phosphorus,” Appl. Phys. Lett., vol. 98, no. 8, 082112-1–082112-3, Feb. 2011. [63] M. J. H. van Dal et al., “Ge n-channel FinFET with optimized gate stack and contacts,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2014, pp. 235–238. [64] E. Simoen et al., “Ion-implantation issues in the formation of shallow junctions in germanium,” Mat. Sci. Semicon. Proc., vol. 9, no. 4–5, pp. 634–639, Oct. 2006. [65] J. K. Kim et al., “Analytical study of interfacial layer doping effect on contact resistivity in metal-interfacial layer-Ge structure,” IEEE Elec. Dev. Lett., vol. 35, no. 7, pp. 705–707, Jul. 2014. [66] H. Wu et al., “Germanium nMOSFETs with recessed channel and S/D: Contact, scalability, interface, and drain current exceeding 1 A/mm,” IEEE Trans. Elec. Dev., vol. 62, no. 5, pp. 1419–1426, May 2015. [67] M. H. Kuo, C. C. Wang, W. T. Lai, T. George, and P. W. Li, “Designer Ge quantum dots on Si: A heterostructure configuration with enhanced optoelectronic performance,” Appl. Phys. Lett., vol. 101, no. 22, pp. 223107-1–223107-5, Nov. 2012. [68] P. W. Li et al., “Method for manufacturing gate stack structure in insta-metal-oxide-semiconductor field-effect transistor,” US 9,299,796, Mar. 29, 2016. [69] Y. J. Yang, W. S. Ho, C. F. Huang, S. T. Chang, and C. W. Liu, “Electron mobility enhancement in strained-germanium n-channel metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 91, no. 10, pp. 102103-1–102103-3, Sep. 2007. [70] M. Chu, Y. Sun, U. Aghoram, and S. E. Thompson, “Strain: A solution for higher carrier mobility in nanoscale MOSFETs,” Annu. Rev. Mater. Res., vol. 39, pp. 203–229, 2009. [71] M. V. Fischettia and S. E. Laux. “Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys,” J. Appl. Phys., vol. 80, no. 4, pp. 2234–2252, Aug. 1996. [72] J. O. Borland, “Low temperature activation of ion implanted dopants: A review,” in Extended Abstracts of International Workshop on Junction Technology (IWJT), Tokyo, Japan, Dec. 2002, pp. 85–88. [73] G. Queirolo et al., “Low temperature dopant activation of BF2 implanted silicon,” J. Electron. Mat., vol. 20, no. 5, pp. 373–378, Mar. 1991. [74] W. T. Lai et al., “A unique approach to generate self-aligned SiO2/Ge/SiO2/SiGe gate-stacking heterostructures in a single fabrication step,” Nanoscale Res. Lett., vol. 10, no. 1, pp. 224-1–224-7, May 2015. [75] D. P. Brunco et al., “Germanium MOSFET devices: Advances in materials understanding, process develo Appl. Surf. Sci pment, and electrical performance,” J. Electrochem. Soc., vol. 155, no. 7, pp. H552–H561, May 2008. Chapter 2 reference [1] W. T. Lai et al., “A unique approach to generate self-aligned SiO2/Ge/SiO2/SiGe gate-stacking heterostructures in a single fabrication step,” Nanoscale Res. Lett., vol. 10, no. 1, pp. 224-1–224-7, May 2015. [2] K. H. Chen, C. Y. Chien, and P. W. Li, “Precise Ge quantum dot placement for quantum tunneling devices,” Nanotechnology, vol. 21, no. 5, pp. 055302-1–055302-9, Feb. 2010. [3] K. H. Chen, C. C. Wang, T. George, and P. W. Li, “The pivotal role of SiO formation in the migration and Ostwald ripening of Ge quantum dots,” Appl. Phys. Lett., vol. 105, no. 12, pp. 122102-1–122102-5, Sep. 2014. [4] K. H. Chen, C. C. Wang, W. T. Lai, T. George, and P. W. Li, “The pivotal role of oxygen interstitials in the dynamics of growth and movement of germanium nanocrystallites,” Cryst. Eng. Comm., vol. 17, no. 33, pp. 6370–6375, Jul. 2015. [5] T. George, P. W. Li, K. H. Chen, K. P. Peng, and W. T. Lai, “‘Symbiotic’ semiconductors: Unusual and counter-intuitive Ge/Si/O interactions,” J. Phys. D: Appl. Phys., vol. 50, no. 10, pp. 105101-1–105101-12, Feb. 2017. [6] R. Tromp, G. W. Rubloff, P. Balk, F. K. LeGoues, and E. J. van Loenen, “High-temperature SiO2 decomposition at the SiO2/Si interface,” Phys. Rev. Lett., vol. 55, no. 21, pp. 2332–2335, Nov. 1985. [7] K. Hofmann and S. I. Raider, “Acceleration factors for the decomposition of thermally grown SiO2 films,” J. Electrochem. Soc., vol. 134, no. 1, pp. 240–244, Jan. 1987. [8] B. J. Hinds, F. Wang, D. M. Wolfe, C. L. Hinkle, and G. Lucovsky, “Investigation of postoxidation thermal treatments of Si/SiO2 interface in relationship to the kinetics of amorphous Si suboxide decomposition,” J. Vac. Sci. Technol. B, vol. 16, no. 4, pp. 2171–2176, May 1998. [9] D. Starodub, E. P. Gusev, E. Garfunkel and T. Gustafsson, “Silicon oxide decomposition and desorption during the thermal oxidation of silicon,” Surf. Rev. Lett., vol. 6, no. 1, pp. 45–52, Feb. 1999. [10] A. A. Stekolnikov and F. Bechstedt, “Shape of free and constrained group-IV crystallites: Influence of surface energies,” Phys. Rev. B, vol. 72, no. 12, pp. 125326-1–125326-9, Sep. 2005. [11] P. H. Liao et al., “Size-tunable strain engineering in Ge nanocrystals embedded within SiO2 and Si3N4,” Appl. Phys. Lett., vol. 105, no. 17, pp. 172106-1–172106-5, Oct. 2014. [12] D. P. Brunco et al., “Germanium MOSFET devices: Advances in materials understanding, process development, and electrical performance,” J. Electrochem. Soc., vol. 155, no. 7, pp. H552–H561, May 2008. [13] K. C. Yang, “Optimization on self-organized Ge-nanoball/SiO2/SiGe gate-stacking heterostructure with interface engineering,” M.S. thesis, Department of Electrical Engineering, National Central University, Taiwan (R.O.C.), 2015. [14] D. Kuzum, A. J. Pethe, T. Krishnamohan, and K. C. Saraswat, “Ge (100) and (111) n- and p-FETs with high mobility and low-T mobility characterization,” IEEE Trans. Elec. Dev., vol. 56, no. 4, pp. 648–655, Apr. 2009. Chapter 3 reference [1] J. Michel, J. Liu, and L. C. Kimerling, “High-performance Ge-on-Si photodetectors,” Nat. Photonic, vol. 4, no. 8, pp. 527–534, Aug. 2010. [2] Y. J. Yang, W. S. Ho, C. F. Huang, S. T. Chang, and C. W. Liu, “Electron mobility enhancement in strained-germanium n-channel metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 91, no. 10, pp. 102103-1–102103-3, Sep. 2007. [3] M. Chu, Y. Sun, U. Aghoram, and S. E. Thompson, “Strain: A solution for higher carrier mobility in nanoscale MOSFETs,” Annu. Rev. Mater. Res., vol. 39, pp. 203–229, 2009. [4] P. H. Liao et al., “Size-tunable strain engineering in Ge nanocrystals embedded within SiO2 and Si3N4,” Appl. Phys. Lett., vol. 105, no. 17, pp. 172106-1–172106-5, Oct. 2014. [5] C. V. Raman and K. S. Krishnan, “A new type of secondary radiation,” Nature, vol. 121, no. 3048, pp. 501–502, Mar. 1928. [6] T. H. Cheng, “Raman scattering of self-organized Ge quantum dot,” M.S. thesis, Department of Physics, National Central University, Taiwan (R.O.C.), 2014. [7] J. E. Chang et al., “Matrix and quantum confinement effects on optical and thermal properties of Ge quantum dots,” J. Phys. D: Appl. Phys., vol. 45, no. 10, pp. 105303-1–150303-9, Feb. 2012. [8] I. R. Lewis and H. Edwards, Handbook of Raman Spectroscopy: From the Research Laboratory to the Process Line. Dekker: New York, 2001. [9] Y. Jie, A. T. S. Wee, C. H. A. Huan, Z. X. Shen, and W. K. Choi, “Phonon confinement in Ge nanocrystals in silicon oxide matrix,” J. Appl. Phys., vol. 109, no. 3, pp. 033107-1–033107-12, Feb. 2011. [10] K. L. Teo, S. H. Kwok, and P. Y. Yu, “Quantum confinement of quasi-two-dimensional E1 excitons in Ge nanocrystals studied by resonant Raman scattering,” Phys. Rev. B, vol. 62, no. 3, pp. 1584–1587, Jul. 2000. [11] S. Lee, S. Huang, G. Conibeer, and M. Green, “In-situ fabrication and characterization of ordered Ge QDs in Si3N4 matrix without barrier layers by rf-magnetron sputtering,” Appl. Surf. Sci., vol. 290, pp. 167–171, Nov. 2013. [12] A. B. Talochkin, V. A. Markov, and V. I. Mashanov, “Inelastic strain relaxation in the Ge quantum dot array,” Appl. Phys. Lett., vol. 91, no. 9, pp. 093127-1–093127-3, Aug. 2007. [13] A. V. Baranov et al., “Polarized Raman spectroscopy of multilayer Ge/Si(001) quantum dot heterostructures,” J. Appl. Phys., vol. 96, no. 5, pp. 2857¬–2863, Jun. 2004. [14] J. R. Huntzinger, A. Mlayah, V. Paillard, A. Wellner, and N. Combe, “Electron-acoustic-phonon interaction and resonant Raman scattering in Ge quantum dots: Matrix and quantum confinement effects,” Phys. Rev. B, vol. 74, no. 11, pp. 115308-1–115308-12, Sep. 2006. [15] Y. M. Yang, L. W. Yang, and P. K. Chu, “Polarized Raman scattering of Ge nanocrystals embedded in a-SiO2,” Appl. Phys. Lett., vol. 90, no. 8, pp. 081909-1–081909-3, Feb. 2007. [16] S. Cosentino et al., “Light harvesting with Ge quantum dots embedded in SiO2 or Si3N4,” J. Appl. Phys., vol. 115, no. 4, pp. 043103-1–043103-7, Jan. 2014. [17] K. W. Adu, H. R. Gutiérrez, U. J. Kim, and P. C. Eklund, “Inhomogeneous laser heating and phonon confinement in silicon nanowires: A micro-Raman scattering study,” Phys. Rev. B, vol. 73., no. 15, pp. 155333-1–155333-9, Apr. 2006. [18] S. Rohmfeld, M. Hundhausen, and L. Ley, “Raman scattering in polycrystalline 3C-SiC: Influence of stacking faults,” Phys. Rev. B, vol. 58., no. 15, pp. 9858–9862, Oct. 1998. [19] Y. H. Gao, Y. Bando, T. Sato, Y. F. Zhang, and X. Q. Gao, “Synthesis, Raman scattering and defects -Ga2O3 of nanorods,” Appl. Phys. Lett., vol. 81, no. 12, pp. 2267–2269, Jul. 2002. [20] F. Cerdeira, C. J. Buchenauer, F. H. Pollak, and M. Cardona, “Stress-induced shifts of first-order Raman frequencies of diamond- and zinc-blende-type semiconductors,” Phys. Rev. B, vol. 5., no. 2, pp. 580–593, Jan. 1972. [21] D. S. Sukhdeo, D. Nam,1, J. H. Kang, M. L. Brongersma, and K. C. Saraswat, “Direct bandgap germanium-on-silicon inferred from 5.7% 〈100〉 uniaxial tensile strain,” Photon. Res., vol. 2, no. 3, pp. A8–A13, Jun. 2014. [22] M. H. Kuo et al., “‘Embedded emitters’: Direct bandgap Ge nanodots within SiO2,” J. Appl. Phys., vol. 120, no. 23, pp. 233106-1–233106-6, Dec. 2016. [23] P. H. Tan, K. Brunner, D. Bougeard, and G. Abstreiter, “Raman characterization of strain and composition in small-sized self-assembled Si/Ge dots,” Phys. Rev. B, vol. 68, no. 12, pp. 125302-1–125302-6, Sep. 2003. [24] J. H. Lin et al., “Strain analysis of Ge/Si(001) islands after initial Si capping by Raman spectroscopy,” J. Appl. Phys., vol. 101, no. 8, pp. 083528-1–083528-4, Apr. 2007. [25] P. H. Liao, K. P. Peng, H. C. Lin, T. George, and P. W. Li, “Single-fabrication-step Ge nanosphere/SiO2/SiGe heterostructures: A key enabler for realizing Ge MOS devices,” Nanotechnology, vol. 29, no. 20, pp. 205601-1–205601-9, Mar. 2018. [26] J. H. Parker, D. W. Feldman, and M. Ashkin, “Raman scattering by silicon and germanium,” Phys. Rev., vol. 155, no. 3, pp. 712–714, Mar. 1967. [27] H. Richter, Z. P. Wang, and L. Ley, “The one phonon Raman spectrum in microcrystalline silicon,” Solid State Commun., vol. 39, no. 5, pp. 625–629, Aug. 1981. [28] F. Pezzoli et al., “Raman spectroscopy determination of composition and strain in Si1-xGex/Si heterostructures,” Mat. Sci. Semicon. Proc., vol. 11, no. 5–6, pp. 279–284, Jan. 1999. [29] K. K. Tiong, P. M. Amirtharaj, F. H. Pollak, and D. E. Aspnes, “Effects of As+ ion implantation on the Raman spectra of GaAs: ‘Spatial correlation’ interpretation,” Appl. Phys. Lett., vol. 44, no. 1, pp. 122–124, Oct. 1983. [30] G. X Cheng, H. Xia, K. J. Chen, W. Zhang, and X. K. Zhang, “Raman measurement of the grain size for silicon crystallites,” Phys. stat. sol. (a), vol. 118, no. 1, pp. K51–K54, Mar. 1990. [31] G. Kanellis, J. F. Morhange, and M. Balkanski, “Effect of dimensions on the vibrational frequencies of thin slabs of silicon,” Phys. Rev. B, vol. 21, no. 4, pp. 1543–1548, Feb. 1980. [32] D. Olego and M. Cardona, “Pressure dependence of Ratnan phonons of Ge and 3C-SiC,” Phys. Rev. B, vol. 25, no. 2, pp. 1151–1160, Jan. 1982. [33] K. H. Chen, C. C. Wang, T. George, and P. W. Li, “The role of Si interstitials in the migration and growth of Ge nanocrystallites under thermal annealing in an oxidizing ambient,” Nanoscale Res. Lett., vol. 9, no. 1, pp. 339-1–339-5, Jul. 2014. [34] T. George et al., “The germanium “Halo”: Visualizing Ge interstitial dynamics in nanocrystallite formation,” Jpn. J. Appl. Phys., vol. 57, no. 10, pp. 105502-1–105502-7, Sep. 2018. [35] J. D. Plummer, M. Deal, and P. D. Griffin, Silicon VLSI technology: Fundamentals, practice, and modeling. Prentice Hall: New Jersey, 2000. [36] H. Ohta, T. Watanabe, and I. Ohdomari, “Strain distribution around SiO2/Si interface in Si nanowires: A molecular dynamics study,” Jpn. J. Appl. Phys., vol. 36, no. 5B, pp. 3277–3282, May 2007. [37] I. D. Sharp et al., “Mechanism of stress relaxation in Ge nanocrystals embedded in SiO2,” Appl. Phys. Lett., vol. 86, no. 6, pp. 063107-1–063107-3, Feb. 2005. [38] A. Wellner et al., “Stress measurements of germanium nanocrystals embedded in silicon oxide,” Appl. Phys. Lett., vol. 94, no. 9, pp. 5639–5642, Nov. 2003. [39] K. J. Chang and M. L. Cohen, “First-principles study of the structural properties of Ge,” Phys. Rev. B, vol. 34, no. 12, pp. 8581–8590, Dec. 1986. [40] Z. Dohčević-Mitrović, Z. V. Popović and M. Šćepanović, “Anharmonicity effects in nanocrystals studied by Raman scattering spectroscopy,” Acta Phys. Pol. A, vol. 116, no. 1, pp. 36–41, Jul. 2009. [41] G. Grimvall, Thermophysical Properties of Materials. Elsevier Science: North Holland, 1999. [42] X. L. Wu et al., “Orange-green emission from porous Si coated with Ge films: The role of Ge-related defects,” J. Appl. Phys., vol. 86, no. 1, pp. 707–709, Jul. 1999. [43] C. W. Tien, “Study of Si interstitials effect on formation and light emitting/detection characteristics of Ge-QD/SiO2/SiGe shell heterostructure,” M.S. thesis, Institute of Electronics, National Chiao Tung University, Taiwan (R.O.C.), 2018. [44] Z. H. Wu, “Formation of Ge quantum dot and shell for Si on insulator applications,” M.S. thesis, Department of Electrical Engineering, National Central University, Taiwan (R.O.C.), 2012. Chapter 4 reference [1] P. H. Liao, K. P. Peng, H. C. Lin, T. George, and P. W. Li, “Single-fabrication-step Ge nanosphere/SiO2/SiGe heterostructures: A key enabler for realizing Ge MOS devices,” Nanotechnology, vol. 29, no. 20, pp. 205601-1–205601-9, Mar. 2018. [2] C. C. Wang, P. H. Liao, M. H. Kuo, T. George, and P. W. Li, “The curious case of exploding quantum dots: Anomalous migration and growth behaviors of Ge under Si oxidation,” Nanoscale Res. Lett., vol. 8, no. 1, pp. 192-1–192-6, Apr. 2013. [3] C. Jaussaud, J. Stoemenos, J. Margail, A. M. Papon, and M. Bruel, “Defects in SIMOX structures: Causes and solutions,” Vacuum, vol. 42, no. 5–6, pp. 341–347, Jan. 1991. [4] F. Pezzoli et al., “Raman spectroscopy determination of composition and strain in Si1-xGex/Si heterostructures,” Mat. Sci. Semicon. Proc., vol. 11, no. 5–6, pp. 279–284, Jan. 1999. [5] J. R. Ligenza, “Effect of crystal orientation on oxidation rates of silicon in high pressure steam,” J. Phys. Chem., vol. 65, no. 11, pp. 2011–2014, Nov. 1961. [6] T. George, P. W. Li, K. H. Chen, K. P. Peng, and W. T. Lai, “‘Symbiotic’ semiconductors: Unusual and counter-intuitive Ge/Si/O interactions,” J. Phys. D: Appl. Phys., vol. 50, no. 10, pp. 105101-1–105101-12, Feb. 2017. [7] K. H. Chen, C. C. Wang, T. George, and P. W. Li, “The role of Si interstitials in the migration and growth of Ge nanocrystallites under thermal annealing in an oxidizing ambient,” Nanoscale Res. Lett., vol. 9, no. 1, pp. 339-1–339-5, Jul. 2014. [8] F. K. LeGoues, R. Rosenberg, T. Nguyen, F. Himpsel, and B. S. Meyerson, “Oxidation studies of SiGe,” J. Appl. Phys., vol. 65, no. 4, pp. 1724–1728, Feb. 1989. [9] D. K. Nayak, K. Kamjoo, J. S. Park, J. C. S. Woo, and K. L. Wang, “Wet oxidation of GeSi strained layers by rapid thermal processing,” Appl. Phys. Lett., vol. 59, no. 4, pp. 369–371, Jul. 1990. [10] H. K. Liou, P. Mei, U. Gennser, and E. S. Yang, “Effects of Ge concentration on SiGe oxidation behavior,” Appl. Phys. Lett., vol. 59, no. 10, pp. 1200–1202, Jun. 1991. [11] W. T. Lai, K. C. Yang, P. H. Liao, T. George, and P. W. L, “Gate-stack engineering for self-organized Ge-dot/SiO2/SiGe-shell MOS capacitors,” Front. Mater., vol. 3, Article 5, pp. 1–9, Feb. 2016. [12] W. T. Lai et al., “A unique approach to generate self-aligned SiO2/Ge/SiO2/SiGe gate-stacking heterostructures in a single fabrication step,” Nanoscale Res. Lett., vol. 10, no. 1, pp. 224-1–224-7, May 2015. [13] C. W. Tien, “Study of Si interstitials effect on formation and light emitting/detection characteristics of Ge-QD/SiO2/SiGe shell heterostructure,” M.S. thesis, Institute of Electronics, National Chiao Tung University, Taiwan (R.O.C.), 2018. [14] H. H. Silvestri, H. Bracht, J. L. Hansen, A N. Larsen, and E. E. Haller, “Diffusion of silicon in crystalline germanium,” Semicond. Sci. Technol., vol. 21, no. 6, pp. 758–762, Apr. 2006. [15] K. J. Kuhn, A. Murthy, R. Kotlyar, and M. Kuhn, “Past, present and future: SiGe and CMOS transistor scaling,” ECS Trans., vol. 33, no. 6, pp. 3–17, 2010. [16] A. E. Dolbak and B. Z. Olshanetsky, “Ge diffusion on Si surfaces,” Cent. Eur. J. Phys., vol. 4, no. 3, pp. 310–317, Sep. 2006. [17] L. Vescan, K. Grimm, and C. Dieker, “Facet investigation in selective epitaxial growth of Si and SiGe on (001) Si for optoelectronic devices,” J. Vac. Sci. Technol. B, vol. 16, no. 3, pp. 1549–1554, May/Jun. 1998. Chapter 5 reference [1] I. H. Chen, “Self-aligned Ge quantum-dot single-hole transistors for nano-thermometry application,” Ph.D. dissertation, Department of Electrical Engineering, National Central University, Taiwan (R.O.C.), 2015. [2] M. Chen and Y. B. Wang, “Overview of SOI technologies in China,” in IEEE International SOI Conference, Foster City, CA, USA, Oct. 2009, pp. 1–4. DOI: 10.1109/SOI.2009.5318787 Chapter 6 reference [1] S. H. Yi, K. S. Chang-Liao, T. Y. Wu, C. W. Hsu, and J. Huang, “High performance Ge pMOSFETs with HfO2/Hf-Cap/GeOx gate stack and suitable post metal annealing treatments,” IEEE Elec. Dev. Lett., vol. 38, no. 5, pp. 544–547, May 2017. [2] W. H. Chang, H. Ota, and T. Maeda, “Gate-first high-performance germanium nMOSFET and pMOSFET using low thermal budget ion implantation after germanidation technique,” IEEE Elec. Dev. Lett., vol. 37. No. 3, pp. 253–256, Mar. 2016. [3] T. Hosoi et al., “Schottky source/drain germanium-based metal-oxide-semiconductor field-effect transistors with self-aligned NiGe/Ge junction and aggressively scaled high-k gate stack,” Appl. Phys. Lett., vol. 107, no. 25, pp. 252104-1–252104-4, Dec. 2015. [4] M. S. Parihar and A. Kranti, “Revisiting the doping requirement for low power junctionless MOSFETs,” Semicond. Sci. Technol., vol. 29, no. 7, pp. 075006-1–075006-11, Apr. 2014. [5] P. H. Liao et al., “Size-tunable strain engineering in Ge nanocrystals embedded within SiO2 and Si3N4,” Appl. Phys. Lett., vol. 105, no. 17, pp. 172106-1–172106-5, Oct. 2014. [6] W. T. Lai et al., “A unique approach to generate self-aligned SiO2/Ge/SiO2/SiGe gate-stacking heterostructures in a single fabrication step,” Nanoscale Res. Lett., vol. 10, no. 1, pp. 224-1–224-7, May 2015. [7] P. H. Liao, K. P. Peng, H. C. Lin, T. George, and P. W. Li, “Single-fabrication-step Ge nanosphere/SiO2/SiGe heterostructures: A key enabler for realizing Ge MOS devices,” Nanotechnology, vol. 29, no. 20, pp. 205601-1–205601-9, Mar. 2018. [8] P. H. Liao, K. P. Peng, H. C. Lin, T. George, and P. W. Li, “Self-organized Ge nanospherical gate/SiO2/Si0.15Ge0.85–nanosheet n-FETs featuring high ON-OFF drain current ratio,” IEEE J. Elec. Dev. Soc., to be published. [9] J. Kim, S. W. Bedell, and D. K. Sadana, “Improved germanium n+/p junction diodes formed by coimplantation of antimony and phosphorus,” Appl. Phys. Lett., vol. 98, no. 8, 082112-1–082112-3, Feb. 2011. [10] M. J. H. van Dal et al., “Ge n-channel FinFET with optimized gate stack and contacts,” in IEDM Tech. Dig., San Francisco, CA, USA, Dec. 2014, pp. 235–238. [11] M. Koike et al., “Diffusion and activation of n-type dopants in germanium,” J. Appl. Phys., vol. 104, no. 2, pp. 023523-1–023523-5, Jul. 2008. [12] H. C. Lin, C. I Lin, and T. Y. Huang, “Characteristics of n-type junctionless poly-Si thin-film transistors with an ultrathin channel,” IEEE Elec. Dev. Lett., vol. 33, no. 1, pp. 53–55, Jan. 2012. [13] C. W. Lee et al., “High-temperature performance of silicon junctionless MOSFETs,” IEEE Trans. Elec. Dev., vol. 57, no. 3, pp. 620–625, Mar. 2010. [14] S. Villa, A. L. Lacaita, L. M. Perron, and Roberto Bez, “A physically-based model of the effective mobility in heavily-doped n-MOSFET’s,” IEEE Trans. Elec. Dev., vol. 45, no. 1, pp. 110–115, Jan. 1998. [15] F. Silveira, D. Flandre, and P. G. A. Jespers, “A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-Insulator micropower OTA,” IEEE J. Solid-State Circ., vol. 31, no. 9, pp. 1314–1319, Sep. 1996. [16] G. V. Luong, S. Trellenkamp, Q. T. Zhao, S. Mantl, and K. K. Bourdelle, “Strained Si nanowire GAA n-TFETs for low supply voltages,” in EUROSOI-ULIS, Bologna, Italy, Jan. 2015, pp. 65–68. [17] J. P. Campbell, K. P. Cheung, J. S. Suehle, and A. Oates, “A simple series resistance extraction methodology for advanced CMOS devices,” IEEE Elec. Dev. Lett., vol. 32, no. 8, pp. 1047–1049, Aug. 2011. [18] H. Wu et al., “Germanium nMOSFETs with recessed channel and S/D: Contact, scalability, interface, and drain current exceeding 1 A/mm,” IEEE Trans. Elec. Dev., vol. 62, no. 5, pp. 1419–1426, May 2015. [19] A. Nazarov et al., Semiconductor-on-insulator materials for nanoelectronics applications. Berlin Heidelberg: Springer, 2011. [20] D. L. Rode, “Electron mobility in Ge, Si, and GaP,” Phys. Stat. Sol. (b), vol. 53, no. 1, pp. 245–254, Sep. 1972. [21] L. Chen, F. Cai, U. Otuonye, and W. D. Lu, “Vertical Ge/Si core/shell nanowire junctionless transistor,” Nano. Lett., vol. 16, no. 1, pp. 420–426, Jan. 2016. [22] P. H. Liao et al., “Self-organized gate stack of Ge nanosphere/SiO2/Si1-xGex enables Ge-based monolithically-integrated electronics and photonics on Si platform,” in VLSI Tech. Dig., Honolulu, HI, USA, Jan. 2018, pp. 157¬–158. Chapter 7 reference [1] M. H. Kuo, C. C. Wang, W. T. Lai, T. George, and P. W. Li, “Designer Ge quantum dots on Si: A heterostructure configuration with enhanced optoelectronic performance,” Appl. Phys. Lett., vol. 101, no. 22, pp. 223107-1–223107-5, Nov. 2012. [2] P. H. Liao et al., “Self-organized gate stack of Ge nanosphere/SiO2/Si1-xGex enables Ge-based monolithically-integrated electronics and photonics on Si platform,” in VLSI Tech. Dig., Honolulu, HI, USA, Jan. 2018, pp. 157¬–158.
指導教授	李佩雯 郭明庭(Pei-Wen Li Ming-Ting Kuo)	審核日期	2019-1-22
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