| 摘要(英) |
As the requirements for synthetic aperture radar (SAR) image resolution are get-ting higher and higher, the sampling frequency and output word-length of ADC keep growing. Both result in the increase of output data quantity. However, the data rate of the link channel between satellites and ground stations is limited. Therefore, the huge amounts of data must be compressed. In this paper, a tunable block floating-point quantizer with fractional exponent is designed to compress the SAR signals so as to maintain good quality. Conventional BFPQ uses exponent to cover the wide dy-namic range of input signals. The exponent of the maximum value of each block is shared among the data in the block and then the threshold is used to derive the quantized results. The representative values in each quantization interval are em-ployed to calculate the error. The error component can be divided into quantization error and saturation error. The performance is evaluated by signal to quantization noise ratio. The proposed tunable BFPQ enlarges the thresholds for exponent and fractional exponent judgement, which can balance the quantization error and the saturation error and thus improve system performance, especially for signals of a large block size. The worlength of the fractional exponent can also be reduced. In our system, the input signal by the ADC can be compressed from 14bits to 2, 3, 4, 6 or 8bits output, and the block size can be set as 8, 16 or 32. In the hardware design, only an extra multiplier is incurred to realize the proposed technique. We use the Xilinx Virtex-7 series of FPGA for verification. In order to pursue higher operating frequen-cy, parallel processing and pipeline techniques are adopted. The measured clock fre-quency reaches 200MHz and can support interleaved ADC with sampling frequency 800MHz. The hardware is also implemented in 40nm CMOS process. The clock fre-quency can be driven up to 250MHz and the power consumption is 7.8mW at 1V supply voltage. |
| 參考文獻 |
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