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姓名 林姿君(Zi-Jun Lin) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 可保留設計風格及繞線行為之類比佈局遷移技術
(A Style-based Analog Layout Migration with Routing Behavior Preservation Technique)相關論文
★ 以基本類比電路架構為基礎的佈局自動化 工具 ★ 實現類比電路仿真的波動數位濾波器架構生成與模擬 檔案 [Endnote RIS 格式]
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摘要(中) 在先進製程的技術中,在電路佈局時必須考慮愈來愈多的非理想效應。由於電路在佈局後模擬(Post-layout simulation)後性能經常大幅地下降,因此傳統類比電路自動化設計工具仍無法被設計者所接受。然而,佈局遷移(Layout migration)是一種比較可行的方法,根據原始電路佈局的拓樸,給定不同的電晶體尺寸或是不同的製程產生新的佈局,該技術不但可以大大減少設計的時間,也可以保留設
計者對類比電路的佈局經驗。
本論文提出一個類比電路佈局遷移的設計自動化流程,目的是將原始佈局的拓撲和設計條件遷移到目標佈局以改善電路性能。對於擺置和繞線遷移的演算法,在之前研究裡所採用的紀錄方式仍有進步的空間,因此在本論文中,使用深度優先 SP 演算法(Depth-First-Search-Sequence pair)記錄原始佈局所有可能的擺置關係,再利用笛卡爾偵測線(Cartesian Detection Line)快速且完整地記錄繞線行為,如同實驗結果所示,將電路從 90nm 遷移到 65nm 製程後,該佈局遷移流程不但可以完整保留佈局的方式和保持良好電路效能,相較之前的電路遷移方式也快速了許多。摘要(英) In modern technology, more and more non-ideal effects should be considered in the circuit layout. Tool-generated analog layouts are still not well accepted by designers since notable performance loss often exists in post-layout simulations. Layout migration is one approach to generate a new layout for given circuits with different device sizes or different technology according to the original layout topology. This technology not only reduces the design time obviously but also preserves the valuable
design expertise of designers.
In this thesis, an automatic analog layout migration flow is proposed. The purpose is to migrate the design constraints and topology of the original layout to the target layout to enhance the circuit performance after layout. In previous work, the placement area and routing completion still have some space to be improved. Therefore, in this thesis, the possible placement of the original layout are recorded by using Depth-First Search-Sequence pair. Routing behavior of original layout are preserved completely with Cartesian Detection Line (CDL). As shown in the experimental results, the proposed algorithm keeps the circuits in a good performance and reduces the design time while migrating the circuits from 90nm to 65nm.關鍵字(中) ★ 佈局遷移
★ 序列對
★ 繞線保留關鍵字(英) ★ Layout Migration
★ Sequence Pair
★ Routing reservation論文目次 Chapter 1 Introduction .......................................... 1
1.1 Analog Design Automation .................................................................... 1
1.2 Previous Works ...................................................................................... 4
1.2.1 Layout Migration with Geometric Constraints .............................. 4
1.2.2 Layout Migration with Regularity Extraction ................................ 6
1.2.3 Layout Migration with Planar Preservation ................................... 8
1.3 Motivation ............................................................................................ 13
1.3.1 Placement for Non-Slicing floorplan ........................................... 13
1.3.2 Incomplete Routing Information .................................................. 15
1.4 Problem Formulation ........................................................................... 16
1.5 Organization ......................................................................................... 17
Chapter 2 Background ........................................ 18
2.1 Sequence Pair ....................................................................................... 18
2.2 Cartesian Detection Lines .................................................................... 21
v
Chapter 3 Style-based Analog Layout Migration .................... 24
3.1 Layout extraction ................................................................................. 25
3.1.1 DFS-SP Placement Topology Extraction ..................................... 25
3.1.2 CDL Construction ........................................................................ 29
3.1.3 Routing Extraction ....................................................................... 30
3.2 Layout migration .................................................................................. 32
3.2.1 SP-based placement migration ..................................................... 32
3.2.2 Routing migration ........................................................................ 36
3.2.3 Routing refinement ...................................................................... 37
Chapter 4 Experimental Results .................................. 40
3.3 Folded-cascode operational amplifier .................................................. 41
3.4 Variable-gained amplifier ..................................................................... 44
Chapter 5 Conclusion .............................................. 47
References ........................................................ 48參考文獻 [1] R.-A. Rutenbar, “Design Automation for Analog: The Next Generation of Tool Challenges,” 1st IBM Academy Conference on Analog Design, Technology, Modeling and Tools, IBM T.J. Waston Research Labs, 2006.
[2] H. Graeb, F. Balasa, R. Castro-Lopez, Y. Chang, F. Fernandez, Po-hung Lin, and M. Strasser, “Analog layout synthesis -recent advances in topological approaches,” in Proc. Design, Automation and Test in Europe, 2009.
[3] P.-H. Lin, Y.-W. Chang and S.-C. Lin, “Analog Placement Based on SymmetryIsland Formulation,” IEEE Trans. on Computer-Aided Design, vol. 28, no. 6, pp.791804, 2009.
[4] L. Xiao, E. F. Y. Young, X. He, and K.-P. Pun, “Practical placement and routing techniques for analog circuit designs,” in Proc. International Conference on Computer Aided Design, pp. 675-679, 2010.
[5] M. Ozdal and R. Hentschke, “Algorithms for Maze Routing with Exact Matching Constraints,” IEEE Trans. on Computer-Aided Design, vol. 33, no. 1, pp. 101-112, 2014.
[6] H.-Y. Chi, H.-Y. Tseng, C.-N. Jimmy Liu, H.-M. Chen, “Performance- Preserved Analog Routing Methodology via Wire Load Reduction,” in Proc. Asia and South Pacific Design Automation Conference, pp. 157-162, 2018.
[7] O.-D.-A. Kazuhiro, A.-P. Louis, and J.-G. Anthony. “A New Methodology for Analog/Mixed-Signal (AMS) SoC Design that Enables AMS Design Reuse and Achieves Full-Custom Performance,” Toshiba/Neolinear 2002
[8] C.-Y. Chin, et al. “Efficient analog layout prototyping by layout reuse with routing preservation,” in Proc. International Conference on Computer Aided Design, pp. 40-47, 2013.
[9] S. Bhattacharya, N. Jangkrajarng, C. -J. R. Shi, “Multilevel symmetry constraint generation for retargeting large analog layouts,” IEEE Tran. on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, issue 6, pp. 245–960, 2006.
[10] X. Zou and S. Nakatake, “Analog Retargeting Constraint Extraction based on Fundamental Circuits and Layout Regularity,” IEEE 2nd New Generation of Circuits and Systems, pp.142-145, 2018
[11] H. Murata, S. Nakatake, K. Fujiyoshi, and Y. Kajitani, “VLSI module placement based on rectangle-packing by Sequence-Pair,” IEEE Trans. on Computer-Aided Design, vol.15, no.12, pp.1518–1524, 1996.
[12] X. Zhang and Y. Kajitani, “Space-planning: Placement and modules with controlled empty area by Single-Sequence,” in Proc. Asia and South Pacific Design Automation Conference, pp.25–30, 2004.
[13] Y.-P. Weng, H.-M. Chen, T.-C. Chen, P.-C. Pan, C.-H. Chen, and W.-Z. Chen, “Fast analog layout prototyping for nanometer design migration,” in Proc. International Conference on Computer Aided Design, pp. 517-522, 2011.
[14] P.-C. Pan, C.-Y. Chin, H.-M. Chen, T.-C. Chen, C.-C. Lee, and J.-C. Lin, “A fast prototyping framework for analog layout migration with planar preservation,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 34 no. 9 pp. 1373-1386, 2015.
[15] Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu, “B*-Trees: A New Representation for Non-Slicing Floorplans,” in Proc. Design Automation Conference, pp. 458-463, 2000.
[16] P.-N. Guo, C.-K. Cheng, and T. Yoshimura. “An O-Tree Representation of Non Slicing Floorplan and Its Applications,” in Proc. Design Automation Conference, pp, 268-273, 1999.
[17] 洪嘉濠,”利用笛卡爾偵測線及R樹保留繞線行為之類比佈局遷移技術”,國 立中央大學電機工程研究所碩士論文, 2018
[18] H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, “Rectangle packing-based module placement,” in Proc. International Conference on Computer Aided Design, pp. 472–479, 1995.
[19] F. Balasa and K. Lampaert, “Symmetry within the sequence-pair representation in the context of placement for analog design,” IEEE Trans. Computer-Aided Design, vol. 19, no. 7, pp. 721-731, 2000.
[20] C. Kodama, K. Fujiyoshi and T, Koga, “A novel encoding method into sequencepair,” IEEE International Symposium on Circuits and Systems, pp.329-332, 2004.
[21] X. Tang, R. Tian, and D. F. Wong, “Fast evaluation of sequence pair in block placement by longest common subsequence computation,” in Proc. Design Automation Test Europe, pp. 106–111, 2000.
[22] Synopsys® Laker®, http://www.synopsys.com
指導教授 周景揚 劉建男(Jing-Yang Jou Chien-Nan Liu) 審核日期 2019-8-19 推文 plurk
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