| 摘要(英) |
In this paper, we use two methods to analysis wafer map. The first method uses deep learning to train a neural network model by actual wafer map data, which is the WM-811K wafer database released by TSMC. The failure patterns can be divided into the following nine categories: Center, Donut, Scratch, Edge-Ring, Edge-Loc, Loc, Near-full, Random, none. Therefore, the trained neural network model can be used to recognize these nine error patterns.
The second method establish a model for judging the randomness of wafer map spatial pattern. First, obtain the wafer format, and then use Matlab simulation to randomly generate the synthetic wafer map. We extract two parameters NBD (Number of Bad Die), NCL (Number of Contiguous Line), and normalize these two parameters to obtain BD and CL. According to different BD, simulate a large number of synthetic wafer maps, generate a complete Boomerangs chart, and use B-score as the criterion for identifying the randomness of the wafer map.
Finally, the two types of methods are combined. The pattern recognition model is used to identify the failure pattern. The B-score and the yield are used to further analyze the wafer after partition from the viewpoint of randomness. In addition, the superposition analysis of the wafer map can be used to determine whether the product has common features. |
| 參考文獻 |
[1] Mill-Jer Wang, Yen-Shung Chang, J.E. Chen, Yung-Yuan Chen, and Shaw-Cherng Shyu, “Yield Improvement by Test Error Cancellation”, Asian Test Symposium (ATS′96), pp.258-260, Nov. 1996.
[2] Ming-Ju Wu, Jyh-Shing Roger Jang, and Jui-Long Chen, “Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets”, IEEE Transactions on Semiconductor Manufacturing, Vol 28, pp. 1-12, Feb. 2015.
[3] Takeshi Nakazawa, and Deepak V. Kulkarni, “Wafer Map Defect Pattern Classification and Image Retrieval Using Convolutional Neural Network”, IEEE Transaction on Semiconductor Manufacturing, Vol 31, pp. 309-314, May. 2018.
[4] Jwu E Chen, Tung-Ying Lu, and Hsing-Chung Liang, “Testing the Spatial Pattern Randomness on Wafer Maps”, VLSI Test Technology Workshop (VTTW), Jul. 2019.
[5] Mengying Fan, Qin Wang, and Ben van der Waal, “Wafer defect patterns recognition based on OPTICS and multi-label classification”, IEEE Advanced Information Management, Communicates, Electronic and Automation Control Conference (IMCEC), pp. 912-915, Oct. 2016.
[6] Bing Liu, “A Fast Density-Based Clustering Algorithm for Large Databases”, International Conference on Machine Learning and Cybernetics, pp. 996-1000, Aug. 2006.
[7] Cheng Hao Jin, Hyuk Jun Na, Minghao Piao, Gouchol Pok, and Keun Ho Ryu, “A Novel DBSCAN-Based Defect Pattern Detection and Classification Framework for Wafer Bin Map”, IEEE Transactions on Semiconductor Manufacturing, Vol. 32, pp. 286-292, May. 2019.
[8] Tsutomu Ishida, Izumi Nitta, Daisuke Fukuda, and Yuzi Kanazawa, “Deep Learning-Based Wafer-Map Failure Pattern Recognition Framework”, International Symposium on Quality Electronic Design (ISQED), pp. 291-297, Apr. 2019.
[9] 林威沅, “Verification of B-score Randomness by Synthetic Random Wafer Maps and Application to Special Patterns”, 碩士論文, 中央大學, 2019.
[10] 侯睿軒, “Model Refinement for the Classifier of the Spatial Pattern Randomness”, 碩士論文, 中央大學, 2019.
[11] 黃昱凱, “Acceleration Core for the Calculation of the Randomness Features of Wafer Maps”, 碩士論文, 中央大學, 2019.
[12] 曾聖翔, “Applications of Randomness and Homogeneity Test to Enhance the Systematic Error Resolution for Wafer Map Analysis”, 碩士論文, 中央大學, 2019. |
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