增強型氮化鎵電晶體之閘極可靠度分析與閘極浮接電性探討

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：104

、訪客IP：3.23.101.82

姓名

秦鎮緯(Zhen-Wei Qin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

增強型氮化鎵電晶體之閘極可靠度分析與閘極浮接電性探討
(Gate Reliability of Schottky p-GaN Gate HEMT and I-V Characteristics of E-mode GaN-Based Transistors under Gate Floating)

相關論文

★ 電子式基因序列偵測晶片之原型	★ 增強型與空乏型砷化鋁鎵/砷化銦鎵假晶格高電子遷移率電晶體: 元件特性、模型與電路應用
★ 使用覆晶技術之微波與毫米波積體電路	★ 注入增強型與電場終止型之絕緣閘雙極性電晶體佈局設計與分析
★ 以標準CMOS製程實現之850 nm矽光檢測器	★ 600 V新型溝渠式載子儲存絕緣閘雙極性電晶體之設計
★ 具有低摻雜Ｐ型緩衝層與穿透型Ｐ＋射源結構之600V穿透式絕緣閘雙極性電晶體	★ 雙閘極金氧半場效電晶體與電路應用
★ 空乏型功率金屬氧化物半導體場效電晶體設計、模擬與特性分析	★ 高頻氮化鋁鎵/氮化鎵高速電子遷移率電晶體佈局設計及特性分析
★ 氮化鎵電晶體 SPICE 模型建立與反向導通特性分析	★ 加強型氮化鎵電晶體之閘極電流與電容研究和長時間測量分析
★ 新型加強型氮化鎵高電子遷移率電晶體之電性探討	★ 氮化鎵蕭特基二極體與高電子遷移率電晶體之設計與製作
★ 整合蕭特基p型氮化鎵閘極二極體與加強型p型氮化鎵閘極高電子遷移率電晶體之新型電晶體	★ 垂直型氧化鎵蕭特基二極體於氧化鎵基板之製作與特性分析

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 ( 永不開放)

摘要(中)

本論文為探討增強型氮化鎵高電子遷移率電晶體(HEMT)的不同閘極偏壓特性研究，根據閘極的操作方式，分成以下兩個部分討論：(1)蕭特基p-GaN閘極氮化鎵電晶體之閘極於高正偏壓下的崩潰機制與機制分析；(2)不同閘極結構商用氮化鎵電晶體之閘極於零伏與浮接狀態下之漏電流比較和原因探討。
現今商用的蕭特基p-GaN閘極氮化鎵電晶體主要的閘極操作偏壓一般來說不超過7 V，由於過高的閘極偏壓將引發高電場效應並造成閘極蕭特基電極與氮化鎵的界面退化。本論文著重在分析不同閘極偏壓下的崩潰機制，透過施加不同的閘極偏壓與環境溫度，探討閘極漏電流的變化。並利用韋伯分布以評估元件可於十年操作前提下的閘極偏壓大小。另進行閘極階段式量測，得到閘極在不同連續偏壓量測下的穩定性。觀察到當閘極於不同高正偏壓條件崩潰後，閘極漏電流會呈現如電阻或二極體般的電性，關於其崩潰後的電性現象，本研究提出等效電路模型進行剖析，主要崩潰原因來自於閘極和源極之間的耐壓性。
論文中另一種研究閘極操作方式為浮接(floating)，透過量測各種商用增強型氮化鎵電晶體在閘極浮接時的基本電性，觀察到當閘極浮接時，元件端點(汲極-源極間)持續增加偏壓下會產生極高的電晶體關閉漏電流。通過比較閘極在零伏與浮接下的電流值，推測在VDS偏壓時，閘極與汲極間的電容會於閘極浮接狀態下產生充電效應，並使載子累積於閘極p-GaN層內，導致元件的開啟使汲極-源極間漏電流(ID)增加(可高達1 mA)。而閘極在零伏下的電流值仍維持在正常的電晶體關閉狀況範圍(10^-10 ~ 10^-11 A)。

摘要(英)

In this study, the gate characteristics of the enhancement-mode AlGaN/GaN high-electron-mobility transistors (HEMTs) has been widely investigated. Based on the gate operation method, it is divided into the following two different section: (1)The gate breakdown mechanism and electrical analysis of Schottky p-GaN Gate HEMT under high positive bias (2) Comparison of the electrical properties of the commercial GaN-based transistors with different gate structure under zero gate bias and gate floating.
Nowadays, the gate operation bias of commercial p-GaN Gate HEMT does not exceed 7 V, because the excessive gate bias will induce high electric field and damage the interface between gate metal and p-GaN layer. This thesis is focused on analyzing the breakdown mechanism through applying different gate bias and various ambient temperature, to observe gate leakage current variety. Afterwards, use numerical method of Weibull distribution to estimate the gate bias after ten years operation. Then, the gate-step stress measurement is also adopted, to obtain the stability of the gate control with continuous gate bias measurement. When the gate breakdown, the change of gate leakage current before and after high voltage stress is observed. The gate leakage current will present like a resistor or a diode after gate breakdown, so the equivalent circuit has been proposed to explain this phenomenon, indicating that the reason of gate breakdown is from the stability between gate and source electrode.
This study also demonstrates the I-V behaviors of various commercial E-mode GaN-based transistors under gate floating and zero gate bias. The high off-state drain current is observed when continuously increase the drain bias under gate floating. Through comparing the current with gate floating and zero gate bias, it is suspected that the capacitance that between gate electrode and drain electrode will charge during the gate floating measurement. The charging effect will induce the carrier accumulate in p-GaN layer, and result in high off-state drain current.

關鍵字(中)

★ 氮化鎵
★ 高電子遷移率電晶體
★ 閘極可靠度
★ 閘極浮接
★ p型氮化鎵

關鍵字(英)

★ GaN
★ HEMT
★ Gate Reliability
★ Gate Floating
★ p-GaN

論文目次

摘要 I
Abstract X
目錄 XII
第一章緒論 1
1.1 前言 1
1.2 三、五族半導體氮化鎵材料特性 2
1.3 加強型氮化鎵電晶體之閘極特性改善文獻回顧 4
1.4 研究動機與目的 16
1.5 論文架構 16
第二章蕭特基p型氮化鎵閘極電晶體之閘極長時間可靠度分析 17
2.1 蕭特基p型氮化鎵閘極電晶體之長時間電性量測 17
2.1.1 閘極可靠度相關文獻回顧 17
2.1.2 元件結構與基本介紹 21
2.1.3 閘極長時間變溫I-V量測 23
2.1.4 韋伯分布分析(Weibull distribution) 28
2.1.5 元件十年壽命預估 31
2.1.6 阿瑞尼斯圖(Arrhenius plot)分析 32
2.1.7 閘極階段式(Gate-Step Stress)量測分析 33
2.2 閘極崩潰機制分析與電性探討 34
2.2.1 漏電流機制介紹 34
2.2.2 崩潰前後之基本電性分析與模擬 36
2.2.3 崩潰後之蕭特基特性漏電流探討 40
2.2.4 崩潰後之歐姆特性漏電流探討 43
2.2.5 蕭特基/歐姆特性漏電流形成之探討 47
2.3 結論 55
第三章增強型氮化鎵元件閘極零伏與浮接之電性分析 56
3.1 商用增強型氮化鎵元件於閘極浮接之電性量測 56
3.1.1 閘極浮接特性相關文獻回顧 56
3.1.2 商用增強型氮化鎵待測元件的基本介紹 59
3.1.3 商用增強型氮化鎵元件之閘極零伏與浮接電性量測 61
3.2 閘極浮接與零伏之特性與機制分析 66
3.3 結論 75
第四章結論 76
參考文獻 77
Publication/Acknowledgement 82

參考文獻

[1] F. Roccaforte, G. Greco, P. Fiorenza, and F. Iucolano, “An overview of normally-off GaN-based high electron mobility transistors,” Materials (Basel), vol. 12, no. 10, May 2019.
[2] Semiconductor TODAY, “GaN to grow at 9% CAGR to over 18% of RF device market by 2020,” Semiconductor TODAY, 2014.
[3] O. Ambacher, J. Smart, J. R. Shealy, N. G. Weimann, K. Chu, M. Murphy, W. J. Schaff, L. F. Eastman, R. Dimitrov, L. Wittmer, M. Stutzmann, W. Rieger, and J. Hilsenbeck, “Two-dimensional electron gases induced by spontaneous and piezoelectric polarization charges in N- and Ga-face AlGaN/GaN heterostructures,” Journal of Applied Physics, vol. 85, no. 6, pp.3222-3233, Mar. 1999.
[4] R. Brown, “A novel AlGaN/GaN based enhancement-mode high electron mobility transistor with sub-critical barrier thickness,” Phd thesis, University of Glasgow, Jul. 2015.
[5] T. Fujii, N. Tsuyukuchi, Y. Hirose, M. Iwaya, S. Kamiyama, H. Amano, and I. Akasaki, “Fabrication of enhancement-mode AlxGa1–xN/GaN junction heterostructure field-effect transistors with p-type GaN gate contact,” Phys. Status Solidi C, vol. 4, no. 7, pp.2708-2711 May 2007.
[6] Y. Cai, Y. Zhou, K. J. Chen, and K. M. Lau, “High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment,” IEEE Electron Device Lett., vol. 26, no. 7, pp.435-437, Jul. 2005.
[7] T. Oka, and T. Nozawa, “AlGaN/GaN recessed MIS-gate HFET with high-threshold-voltage normally-off operation for power electronics applications,” IEEE Electron Device Lett., vol. 29, no. 7, pp.668-670, Jul. 2008.
[8] Y. Xu, S. Cristoloveanu, M. Bawedin, K.-S. Im, and J.-H. Lee, “Performance improvement and sub-60 mV/decade swing in AlGaN/GaN FinFETs by simultaneous activation of 2DEG and sidewall MOS channels,” IEEE Trans. Electron Devices, vol. 65, no. 3, pp.915-920, Mar. 2018.
[9] K. J. Chen, O. Haberlen, SLidow, C. L. Tsai, T. Ueda, Y. Uemoto, and Y. Wu, “GaN-on-Si power technology: Devices and applications,” IEEE Trans. Electron Devices, vol. 64, no. 3, pp.779-795, Mar. 2017.
[10] Y. Uemoto, M. Hikita, H. Ueno, H. Matsuo, H. Ishida, M. Yanagihara, T. Ueda, T. Tanaka, and D. Ueda, “Gate injection transistor (GIT)—a normally-off AlGaN/GaN power transistor using conductivity modulation,” IEEE Trans. Electron Devices, vol. 54, No. 12, pp.3393-3399, Dec. 2007.
[11] O. Hilt, A. Knauer, F. Brunner, E. Bahat-Treidel, and J. Würfl, “Normally-off AlGaN/GaN HFET with p-type GaN gate and AlGaN buffer,” 2010 22nd International Symposium on Power Semiconductor Devices & IC′s (ISPSD), pp.347-350, 2010.
[12] I. Hwang, J. Oh, H. S. Choi, J. Kim, H. Choi, J. Kim, S. Chong, J. Shin, and U. I. Chung, “Source-Connected p-GaN Gate HEMTs for Increased Threshold Voltage,” IEEE Electron Device Lett., vol. 34, no. 5, pp.605-607, May 2013.
[13] F. Lee, L.-Y. Su, C.-H. Wang, Y.-R. Wu, and J. Huang, “Impact of gate metal on the performance of p-GaN/AlGaN/GaN high electron mobility transistors,” IEEE Electron Device Lett., vol. 36, no. 3, pp.232-234, Mar. 2015.
[14] K. Tanaka, T. Morita, H. Umeda, S. Kaneko, M. Kuroda, A. Ikoshi, H. Yamagiwa, H. Okita, M. Hikita, M. Yanagihara, Y. Uemoto, S. Takahashi, H. Ueno, H. Ishida, M. Ishida, and T. Ueda, “Suppression of current collapse by hole injection from drain in a normally-off GaN-based hybrid-drain-embedded gate injection transistor,” Appl. Phys. Lett., vol. 107, no. 16, pp.163502, Oct. 2015.
[15] Y. N. Zhong, W. C. Ho, Y. C. Lai, Y. M. Hsin, Y. T. Hsieh, H. H. Tsai, and Y. Z. Juang, “Improved Device Performance by Integrating Schottky p-GaN Gate Diode and E-mode p-GaN Gate HEMT for 650 V Application,” The 9th Asia-Pacific Workshop on Widegap Semiconductor (APWS2019), Nov. 2019.
[16] X. Liu, H. C. Chiu, C. H. Liu, H. L. Kao, C. W. Chiu, H. C. Wang, J. Ben, W. He, and C. R. Huang, “Normally-off p-GaN gated AlGaN/GaN HEMTs using plasma oxidation technique in acccess region,” IEEE J. Electron Devices Society, vol. 8, pp.229-234, Feb. 2020.
[17] C. H. Liu, H. C. Chiu, and C. C. Chiu, “High-gate-voltage-swing region of normally-off p-GaN MIS-HEMT with ALD-grown Al2O3/AlN gate insulator layer,” 2020 International Conference on Compound Semiconductor Manufacturing Technology (CS-MANTECH), 2020.
[18] C. Wang, M. Hua, J. Chen, S. Yang, Z. Zheng, J. Wei, L. Zhang, and K. J. Chen, “E-Mode p-n junction/AlGaN/GaN (PNJ) HEMTs,” IEEE Electron Device Lett., vol. 41, no. 4, pp.545-548, Apr. 2020.
[19] L. Zhang, Z. Zheng, S. Yang, W. Song, J. He, and K. J. Chen “p-GaN gate HEMT with surface reinforcement for enhanced gate reliability,” IEEE Electron Device Lett., vol. 42, no. 1, pp.22-25, Jan. 2021.
[20] C. H. Liu, H. C. Chiu, H. C. Wang, H. L. Kao, and C. R. Huang, “Improved gate reliability normally-off p-GaN/AlN/AlGaN/GaN HEMT with AlGaN cap-layer,” 2021 International Conference on Compound Semiconductor Manufacturing Technology (CS-MANTECH), 2021.
[21] M. Tapajna, O. Hilt, E. Bahat-Treidel, J. Wurfl, and J. Kuzunik, “Gate reliability investigation in normally-off p-Type-GaN cap/AlGaN/GaN HEMTs under forward bias stress,” IEEE Electron Device Lett., vol. 37, no. 4, pp. 385-388, Apr. 2016.
[22] A. N. Tallarico, S. Stoffels, P. Magnone, N. Posthuma, E. Sangiorgi, S. Decoutere, and C. Fiegna, “Investigation of the p-GaN Gate Breakdown in Forward-Biased GaN-Based Power HEMTs,” IEEE Electron Device Lett., vol. 38, no. 1, pp.99-102, Jan. 2017.
[23] Y. Shi, Q. Zhou, W. Xiong, X. Liu, X. Ming, Z. Li, W. Chen, and B. Zhang, “Observation of self-recoverable gate degradation in p-GaN AlGaN/GaN HEMTs after long-term forward gate stress: The trapping & detrapping dynamics of hole/electron,” The 31st International Symposium on Power Semiconductor Devices & ICs (ISPSD), May. 2019
[24] G. Zhou, F. Zeng, Y. Jiang, Q. Wang, L. Jiang, G. Xia, and H. Yu, “Determination of the gate Breakdown mechanisms in p-GaN Gate HEMTs by multiple-gate-sweep measurements,” IEEE Trans. Electron Lett., vol. 68, no. 4, pp.1-6, Apr. 2021.
[25] Keysight, Keysight B1505A Power Device Analyzer/Curve Tracer. Keysight, 2011
[26] M. Ruzzarin, M. Meneghini, A. Barbato, V. Padovan, O. Haeberlen, M. Silvestri, T. Detzel, G. Meneghesso, and E. Zanoni, “Degradation mechanisms of GaN HEMTs with p-Type gate under forward gate bias overstress,” IEEE Trans. Electron Lett., vol. 65, no. 7, Jul. 2018.
[27] J. He, G. Tang, and K. J. Chen, “VTH instability of p-GaN gate HEMTs under static and dynamic gate stress,” IEEE Electron Device Lett., vol. 39, no. 10, Oct. 2018.
[28] Silvaco, Silvaco Atlas User’s Manual Device Simulation Software, Aug. 2016.
[29] Y. Xin, W. Chen, R. Sun, Y. Shi, C. Liu, Y. Xia, F. Wang, X. Xu, Q. Shi, Y. Wang, X. Deng, Q. Zhou, Z. Li, B. Zhang, “Electrostatic discharge (ESD) behavior of p-GaN HEMTs,” The 32nd International Symposium on Power Semiconductor Devices & ICs (ISPSD), Sep. 2020.
[30] H. Xu, J. Wei, R. Xie, Z. Zheng, and K. J. Chen, “A SPICE-Compatible Equivalent-Circuit Model of Schottky Type p-GaN Gate Power HEMTs with Dynamic Threshold Voltage,” The 32nd International Symposium on Power Semiconductor Devices & ICs (ISPSD), Sep. 2020.
[31] GaN System “GS66508B Bottom-side cooled 650 V E-mode GaN transistor datasheet,” 2004
[32] Infineon “IGT60R070D1 datasheet,” no Version 2.12, 2012
[33] Transphorm “TPH3212PS datasheet,” p.1-13, 2017
[34] Keysight, The Parametric Measurement Handbook, 4th Edition, 2017
[35] W. C. Liao, J. I. Chyi, and Y. M. Hsin, “Trap-profile extraction using high-voltage capacitance–voltage measurement in AlGaN/GaN heterostructure field-effect transistors with field plates,” IEEE Trans. Electron Devices, vol. 62, no. 3, pp.835-839, Mar. 2015.
[36] Y. Wang, M. Hua, G. Tang, J. Lei, Z. Zheng, J. Wei, and K. J. Chen, “Dynamic OFF-State Current (Dynamic IOFF) in p-GaN Gate HEMTs With an Ohmic Gate Contact,” IEEE Electron Device Lett., vol. 39, no. 9, pp.1366-1369, Sep. 2018.
[37] M. Hua, J. Chen, C. Wang, L. Liu, L. Li, J. Zhao, Z. Jiang, J. Wei, L. Zhang, Z. Zheng, and K. J. Chen, “E-mode p-GaN Gate HEMT with p-FET Bridge for Higher VTH and Enhanced VTH Stability,” 2020 IEEE International Electron Devices Meeting (IEDM), pp.23.1.1-23.1.4., Dec. 2020

指導教授

辛裕明(Yue-Ming Hsin)

審核日期

2021-9-14

推文