| 摘要(英) |
In this paper, we focus on two parts, one is the analysis of similarity model and the other is the application of similarity clustering analysis. In this paper, we first discuss the similarity analysis. The experimental subjects are synthetic wafers with different yields and different numbers of diesize, and we define the similarity determination formula and the model of similarity values and yields under the normal distribution.
The wafers we used are from the WM-811K wafer database provided by TSMC, and the error patterns can be classified into the following nine categories: Center, Donut, Scratch, Edge-Ring, Edge-Loc, Loc, Near-Full, Random, and None.
Finally, the performance ratios for different wafer sizes were calculated separately, and the larger the wafer, the more computation time was required.
Finally, the similarity formula and cluster analysis are used to determine the error patterns of synthetic wafers and real wafers to understand their characteristics and finally to determine the characteristics of the product. |
| 參考文獻 |
[1] Ming-Ju Wu, Jyh-Shing Roger Jang, and Jui-Long Chen, “Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets”, IEEE Transactions on Semiconductor Manufacturing, Vol 28, pp. 1-12, Feb. 2015.
[2] Mill-Jer Wang, Yen-Shung Chang, J.E. Chen, Yung-Yuan Chen, and Shaw-Cherng Shyu, “Yield Improvement by Test Error Cancellation”, Asian Test Symposium (ATS′96), pp.258-260, Nov. 1996.
[3] Takeshi Nakazawa, and Deepak V. Kulkarni, “Wafer Map Defect Pattern Classification and Image Retrieval Using Convolutional Neural Network”, IEEE Transaction on Semiconductor Manufacturing, Vol 31, pp. 309-314, May. 2018.
[4] Jwu E Chen, Tung-Ying Lu, and Hsing-Chung Liang, “Testing the Spatial Pattern Randomness on Wafer Maps”, VLSI Test Technology Workshop (VTTW), Jul. 2019.
[5] Ya-Hsuan Wu, “Wafer Map Partition Analysis to Enhance Systematic Error Resolution”, M.S. thesis, Dept. Electron. Eng., National Central University, Taoyuan, Taiwan (R.O.C.), Apr. 2018.
[6] Cheng-Yan Wu, “Applications of Yield and Randomness Homogeneity Tests to Wafer Map Analysis”, M.S. thesis, Dept. Electron. Eng., National Central University, Taoyuan, Taiwan (R.O.C.), Jan. 2020.
[7] Tung-Ying Lu, “Application of Wafer Map Partition Analysis to Enhance the Salient Pattern Identification”, M.S. thesis, Dept. Electron. Eng., National Central University, Taoyuan, Taiwan (R.O.C.), Oct. 2019.
[8] Feng Zhou, Fernando De la Torre, Jessica K. Hodgins, “Hierarchical Aligned Cluster Analysis for Temporal Clustering of Human Motion”, IEEE Transactions on Pattern Analysis and Machine Intelligence, Vol 35, pp. 582-596, Mar. 2013.
[9] Ming-Ju Wu, Jyh-Shing R. Jang, Jui-Long Chen, “Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets”, IEEE Transactions on Semiconductor Manufacturing, Vol 28, pp. 1-12, Feb. 2015. |
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