| 姓名 |
黃紹勛(Shao-Syun Huang)
查詢紙本館藏 |
畢業系所 |
電機工程學系 |
| 論文名稱 |
應用於2.5G/5GBASE-T乙太網路傳收機之高成本效益迴音消除器
(A High Cost-Effective Echo Canceller Design for 2.5G/5GBASE-T Ethernet Transceiver)
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| 相關論文 | |
| 檔案 |
 [Endnote RIS 格式]
[Bibtex 格式]
 [相關文章]  [文章引用]  [完整記錄]  [館藏目錄]  至系統瀏覽論文 ( 永不開放)
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| 摘要(中) |
在有線通訊中，由於雙絞線全雙工傳輸的迴音干擾現象，接收端之訊號與雜訊比受到嚴重影響，顯示了迴音消除器之必要性。傳統上迴音消除方法為使用自適應濾波器，複製迴音路徑之通道效應，使得訊號經過迴音路徑與訊號經過迴音消除器相同，進而將迴音扣除。一般高成本之作法為使用有限脈衝響應 ( Finite Impulse Response, FIR ) 濾波器，隨著通道效應拉長，有限脈衝響應濾波器需跟著拉長才能達到可接受之回音扣除效果，意即需要之乘法器數量也會隨之增長，造成電路成本提高，因此在有達到性能要求之模擬結果下，降低電路成本越來越受到重視。本論文所採用之迴音通道模型，在尾段的部分有因為近端 ( Near end ) 與遠端 ( Far end ) 傳輸不匹配所造成小幅度之反射波 ( Reflection ) ，且反射波位置會因通道長度而有所改變，因此使得現存一些文獻所提出之方法無法達到期望之迴音扣除效果，抑或是電路成本無法大幅改善。本論文除了將文獻所提供之方法混和 ( Hybrid ) 有限脈衝響應 ( FIR ) 無限脈衝響應 ( Infinite Impulse Response, IIR ) 濾波器與插植濾波器 ( Interpolator filter ) 進行模擬分析，並針對所使用之迴音通道提出改良之架構，使得迴音扣除效果在要求範圍內，電路成本之節省相較於傳統使用有限脈衝響應濾波器達到超過70%的效果，且對使用插值濾波器，與改良之混和有限脈衝響應與無限脈衝響應濾波器，也有59%與11%之節省。關於硬體實現，使用Verilog HDL描述與模擬，透過SMIMS VeriEnterprise Xilinx FPGA驗證電路功能，再經由Design compiler與IC compiler來驗證在製程為TSMC-40nm下之電路功能。 |
| 摘要(英) |
In wireline communications, the signal-to-noise ratio at the receiving end is affected by the echo interference of twisted-pair full-duplex cables transmission. In order to realize the necessary of echo canceller, the traditional method of echo cancellation uses an adaptive filter to copy the echo channel effect, so that signal passes through the echo path is the same as that passes through the echo canceller, and then the echo is subtracted. In the literature, high-cost method is to use Finite Impulse Response (FIR) filter. Along with channel effect becomes longer, the finite impulse response filter needs to be elongated to achieve an acceptable performance, which means the number of multipliers required. It will also result in an increase of cost. Therefore, with the acceptable performance, reducing circuit cost is more and more important.
In this work, in addition to simulate the methods provided in the literature which called the Hybrid FIR-IIR (Infinite Impulse Response) filter, and Interpolation filter, we also proposed an improved method which can still maintain the required performance, and compared it with the traditional method that used FIR filter, the circuit cost saving can reach more than 70%, as for comparing with Interpolation filter, and Hybrid FIR-IIR filter, there are also 59% and 10% saving.
Regarding the hardware implementation, first the Verilog HDL description is employed and the related simulations ,are conducted, then verify the circuit function through SMIMS VeriEnterprise Xilinx FPGA, and finally verify the circuit function under the TSMC-40nm process through Design Compiler and IC Compiler. |
| 關鍵字(中) |
★ 迴音消除器
★ 有限脈衝響應濾波器
★ 無限脈衝響應濾波器
★ 乙太網路
★ 插值濾波器
★ 成本效益 |
關鍵字(英) |
★ Echo canceller
★ FIR filter
★ IIR filter
★ Ethernet
★ AIFIR filter
★ Cost-Effective |
| 論文目次 |
目錄
摘要 i
Abstract ii
圖目錄 vii
表目錄 x
第一章 緒論 1
1.1背景 1
1.2研究動機 1
1.3論文貢獻 2
第二章 迴音消除器電路介紹 3
2.1迴音消除器電路系統概要 3
2.2有限脈衝響應電路架構 4
2.3無限脈衝響應電路架構 6
第三章 迴聲消除器演算法介紹 8
3.1最小均方（LMS）演算法 8
3.2延遲最小均根(Delayed-LMS) 10
第四章 文獻已提出之架構分析與模擬 14
4.1混和有限脈衝響應與無限脈衝響應濾波器[4] 14
4.1.1電路架構 14
4.1.2模擬結果 16
4.2插值濾波器[6][7] 18
4.2.1電路架構 18
4.2.2模擬結果 19
4.3混和型濾波器連接有限脈衝響應濾波器 22
4.3.1電路架構 22
4.3.2模擬結果 23
第五章 暫存元件數量決定方法 26
第六章 提出之改良架構與模擬結果 30
6.1混和型濾波器連接插值濾波器電路架構 30
6.1.1 Main canceller內部架構 31
6.1.2 Tail canceller內部架構 32
6.1.3 Reflection canceller內部架構 33
6.2模擬環境 34
6.2.1十公尺模擬環境 34
6.2.2二十公尺模擬環境 34
6.2.3三十公尺模擬環境 35
6.2.4四十公尺模擬環境 35
6.2.5五十公尺模擬環境 36
6.2.6六十公尺模擬環境 36
6.2.7七十公尺模擬環境 37
6.2.8八十公尺模擬環境 37
6.2.9九十公尺模擬環境 38
6.2.10一百公尺模擬環境 38
6.3模擬結果 39
6.3.1十公尺模擬結果 39
6.3.2二十公尺模擬結果 39
6.3.3三十公尺模擬結果 40
6.3.4四十公尺模擬結果 40
6.3.5五十公尺模擬結果 41
6.3.6六十公尺模擬結果 41
6.3.7七十公尺模擬結果 42
6.3.8八十公尺模擬結果 42
6.3.9九十公尺模擬結果 43
6.3.10一百公尺模擬結果 43
6.3.11十到一百公尺長度之模擬結果 44
6.4架構比較 46
第七章 電路架構與晶片實現 47
7.1 電路設計流程 47
7.2硬體電路介紹 48
7.2.1無限脈衝響應濾波器架構 48
7.2.2無限脈衝響應濾波器架構 49
7.3模擬驗證 50
7.4晶片設計結果 51
7.4.1佈局圖 51
7.4.2模組分布 52
7.4.3錯誤覆蓋率 54
7.4.4 LVS驗證結果 54
7.4.5 CHIP功率消耗分佈 55
7.4.6 CHIP 總結 56
第八章 結論與未來展望 57
參考文獻 58
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| 參考文獻 |
[1] N. Verhoeckx, H. van den Elzen, F. Snijders and P. van Gerwen, “Digital echo cancellation for baseband data transmission,” IEEE Trans. on Acoustics, Speech, and Signal Processing, Vol.27, pp. 768-781, Dec 1979.
[2] N. J. Fiege, “Multirate digital signal processing: multirate systems, filter banks, wavelets”, 1994.
[3] Y. Sato, “A method of self-recovering equalization for multi-level amplitude modulation,” IEEE Trans. Commun., Vol. COM-23, NO. 6, pp. 679-682, June 1975.
[4] A. F. Shalash, "Hybrid FIR-IIR Adaptive Echo Canceller for Wireline Applications," Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005., 2005, pp. 364-368, doi: 10.1109/ACSSC.2005.1599769.
[5] Fan Hong and W. K. Jenkins, "An investigation of an adaptive IIR echo canceller: advantages and problems," in IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 36, no. 12, pp. 1819-1834, Dec. 1988, doi: 10.1109/29.9027.
[6] Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme from https://scholars.lib.ntu.edu.tw/handle/123456789/427697.
[7] Shou-Sheu Lin and Wen-Rong Wu, "A low-complexity adaptive echo canceller for xDSL applications," in IEEE Transactions on Signal Processing, vol. 52, no. 5, pp. 1461-1465, May 2004, doi: 10.1109/TSP.2004.826155. |
| 指導教授 |
薛木添(Muh-Tian Shiue)
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審核日期 |
2021-10-27 |
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