一個可靠的靜態隨機存取記憶體內運算結構: 設計指南與耐老化策略研究

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姓名

張維(Wei Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

一個可靠的靜態隨機存取記憶體內運算結構: 設計指南與耐老化策略研究
(A Reliable SRAM In-Memory Computing Architecture: Design Guidelines and Aging-Tolerance Strategies)

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至系統瀏覽論文 (2026-11-24以後開放)

摘要(中)

記憶體內運算 (In-memory computing, IMC) 能夠透過類比訊號的行為模式在記憶體內部直接做資料的處理，此方法提供了既快速又有效率的布林邏輯運算 (Boolean logic computation)。在眾多記憶體內運算架構中，有一種架構是以靜態隨機存取記憶體 (Static Random Access Memory, SRAM) 為基礎，其行為是使用觀察放電的幅度來實現不同的布林邏輯運算。
從前述可得知，IMC的運算基本上是以類比的行為來進行，所以IMC對於電壓或是電流的變異是十分敏感，因此IC製程、電壓、溫度等變異 (PVT variation) 以及老化效應 (Aging effects) 會對記憶體內部運算造成嚴重的影響，甚至是運算結果的正確性。因此，如何改善記憶體內部運算結果的正確性並延長系統的壽命就成為一個需要被解決的問題。
在本篇論文中，我們主要針對正偏壓溫度不穩定性 (Positive Bias Temperature Instability, PBTI) 老化效應對記憶體內部運算所造成的影響。在觀察不同數量的列對於記憶體內部運算架構的不同效果之後，我們提出了建構基於SRAM的記憶體內部運算架構設計指南以及抗老化效應的方法。其中包含使用Supplemental Transistors (ST)以及透過調節RWL寬度來改善受到PBTI效應的8T SRAM的IMC架構的方法，此耐老化方法也適用於其他同類型的SRAM IMC架構。另外，為了得知記憶體內部的健康狀況，我們提出了一個自我檢測的方法，可得知記憶體內部各列的老化嚴重程度，配合提出的抗老化方法，達到延長系統壽命的目標。本論文的實驗結果顯示我們所提出的方法對於不同列的IMC架構皆可行，並能使得系統的壽命有明顯的延長。

摘要(英)

In-memory computing (IMC) has been proposed to overcome the well-known von-Neumann bottleneck. IMC can directly accomplish data processing inside memory arrays, and it provides efficient and fast operations such as Boolean logic computation. With various IMC architectures, one of such an architecture is SRAM-based IMC, which uses the voltage amplitude to realize Boolean logic functions such as NOR, NAND and XOR.
Based on the previous description, we know that IMC operation is sensitive to the deviations. Therefore, the PVT variations as well as aging effects will seriously influence the accuracy of IMC results. Moreover, we observe that there are difference between different rows of memories.
In this thesis, we concentrate on the Positive Bias Temperature Instability (PBTI) effect, which will eventually cause the incorrect IMC results. Hence we provide a PBTI-aware SRAM IMC architecture. To achieve this goal, we propose two aging tolerance methods to maintain the correctness of IMC results in SRAM IMC architecture. Furthermore, we develop a self-testing aging detection method to determine the health condition of each row in memory. Finally, we give the guidelines for constructing such IMC architectures. Experimental results show the IMC architecture could still work correctly under PBTI effect with our methods. Moreover, the system lifetime can further be extended.

關鍵字(中)

★ 靜態存取記憶體
★ 記憶體內運算
★ 正偏壓溫度不穩定性
★ 抗老化方法
★ 老化偵測方法

關鍵字(英)

★ SRAM
★ In-Memory Computing
★ Positive Bias Temperature Instability
★ PBTI
★ Aging Tolerance Method
★ Aging Detection Method

論文目次

摘要 i
Abstract ii
致謝 iii
Table of Contents iv
Table of Figures vi
Table of Tables viii
Chapter 1 Introduction 1
Chapter 2 Preliminaries 7
2.1 6T SRAM Read and Write Operation 7
2.2 8T SRAM In-memory Computing 9
2.3 PBTI Effect 12
2.4 PBTI Model 13
2.5 8T SRAM In-Memory Computing Architecture with PBTI Effect 14
Chapter 3 Problem Formulation 16
Chapter 4 Framework 18
4.1 Aging Detection Method 19
4.2 Supplemental Transistor Approach 21
4.3 Pulse Width of RWLIMC Adjustment 23
4.4 Summaries for Design Guidelines 26
Chapter 5 Experimental Result 29
5.1 Supplemental Transistor Approach 29
5.2 Pulse Width of RWLIMC Adjustment 32
5.3 Extended Lifetime Comparison 34
Chapter 6 Conclusions 36

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指導教授

陳聿廣(Yu-Guang Chen)

審核日期

2021-11-26

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