| 摘要(英) |
This study uses a statistically developed IC test model with test yield and test quality as
the criteria for evaluating test results. The model is based on the normative distribution
and incorporates a number of parameters that express manufacturability and testability,
and is supplemented by the concept of test shields and re-testing, which proposes a new
testing mechanism.
Among them, the re-testing includes the re-testing scheme and the multi-testing scheme.
However, when using the aforementioned mathematical model, it is not possible to
quickly derive suitable test parameters, so we analyze it and obtain a recursive expression.
Based on this mathematical model, the iteration method and the bisection method are
further deduced from the automatic-guardbanding test system, which can quickly derive
the corresponding test specifications with a fixed test quality and frequency.
The random and unstable characteristics of the test and manufacturing of the two
test solutions in the retest make it impossible for us to evaluate the advantages and
disadvantages of the two solutions. But under the comparison of a large amount of data,
the repeat test method will have a better test yield under the same test quality requirements. |
| 參考文獻 |
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[2] International Technology Roadmap for Semiconductors 2.0., System Integration.
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[5] C. -H. Yeh and J. -E. Chen, “Multiple Tests for Maximizing the Yield without
Degrading Quality,” in Proc. of the 3rd VLSI Test Technology Workshop, pp.76-81,
Taiwan, 2009.
[6] J. -E. Chen and C. -H. Yeh, “Test Guardbanding for Yield and Quality Estimation,”
in Proc. of the. International Test Synthesis Workshop, pp. 114-115、USA, 2004.
[7] C. L. Henderson, R. H. Williams, and C. F. Hawkins, “Economic Impact of Type I
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(ITC), pp. 441-451, Baltimore, MD、USA, 1992.
[8] West. B. G. 1999, “Accuracy requirements in at-speed functional test,” International
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[9] C. -H. Yeh and J. -E. Chen, “Repeated Testing Applications for Improving the IC Test
Quality to Achieve Zero Defect Product Requirements,” Journal of Electronic Testing,
Vol 35, 4, pp. 459–472, 2019. |
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