應用於通訊系統的內嵌式數位訊號處理器架構

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姓名

劉金茂(Jin-Mao Liu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於通訊系統的內嵌式數位訊號處理器架構
(Embedded DSP Core Architecture for Communication Applications)

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摘要(中)

今天, 數位訊號處理器(DSP Procesor)是許多通信系統和嵌入的系統的心臟。本論文主要是研究發展一種低價位,可以重複使用,開發時間短,並且可以根據顧客的規格產生數位訊號處理器處理機的架構。
在本論文中,我們根據近幾年所提出有關數位訊號處理器的架構及參數化訊號處理器的設計方法等相關期刊論文,設計出符合我們所要的數位訊號處理器的架構,並且根據我們的需求提出此處理器的定址模式與指令集,並且解決了管線化架構(Pipeline Architecture)
所遭遇的問題。
最後,整顆晶片用Verilog語言描述完成,並且經過Synopsys公司所提供
的數位電路合成工具完成整顆晶片的模擬,本晶片總共使用27915.418 gate counts,並且工作於100MHz的速度。

摘要(英)

Today, DSP processors are at the heart of many communication systems and embedded systems. The object of this thesis is to develop a DSP processor architecture that is suitable to be parameterized by user specification to obtain a DSP processor that has the characteristics of low cost, reusable, and short time-to-market.
In this thesis, we survey several DSP processor architectures and the scheme of parameterized DSP processor core in recent years. Then, we propose a DSP processor architecture that can be parameterized. In addition, we also address the addressing modes in the DSP processor according to the characteristic of DSP algorithm. For high performance DSP processor, we also modify the architecture of MAC unit and design suitable pipeline stages in the processor. We also propose the solutions of pipeline hazard to resolve the pipeline stall.
Finally, the DSP processor is described with Verilog hardware description language and synthesized by Synopsys. From the synthesis reports, the total gate counts are 27915.418 gates and can operate in 100MHz.

關鍵字(中)

★ 數位訊號處理器

關鍵字(英)

★ DSP Processor

論文目次

Contents
1. Introduction
1.1Background and Motivation
1.2Thesis organization
2. Overview and Modification of the DSP Architecture
2.1Introduction
2.1.1 Von Neumann architecture
2.1.2 Harvard architecture
2.1.3 Modified Harvard architecture
2.2 The characteristics of DSP algorithm
2.2.1 The DSP algorithms for communication applications
2.2.2 Using dedicated hardware to implement DSP algorithm
2.3 Parameterized DSP core
2.3.1 The parameters of DSP core
2.3.2 The special functions of DSP core
2.4 Summary
3. Instruction sets and addressing modes
3.1Introduction
3.2Instruction types
3.2.1 TI C54X Instruction sets
3.2.2 Arithmetic and Multiplication instructions
3.2.3 Logic operation instructions
3.2.4 Comparison instructions
3.2.5 Hardware loop instructions
3.2.6 Branching and Subroutine call and return instructions
3.2.7 Special function instructions
3.2.8 Summary
3.3Addressing Modes
3.3.1 Direct addressing mode
3.3.2 Indirect/register addressing mode
3.3.3 Immediate/Absolute addressing mode
3.3.4 Register addressing mode
3.4Summary
4. Pipeline Architecture
4.1Introduction
4.2Pipeline stages
4.2.1 Instruction fetch unit
4.2.2 Instruction decode unit
4.2.3 Operand fetch unit
4.2.4 Execute 1 unit
4.2.5 Execute 2 unit
4.2.6 Write back unit
4.3 Pipeline hazards problem and solutions
4.3.1 Structural hazard
4.3.2 Data hazard
4.3.3 Control hazard
4.5 Summary
5. Design of Data Path Unit
5.1 Introduction
5.2 Overview of the Data Path Function Units
5.3 Multiply-and-Accumulate Unit
5.3.1 Traditional multiply-and-accumulate unit
5.3.2 Modified multiply-and-accumulate unit
5.4 Summary
6. Instruction sets simulation
7. Conclusions

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指導教授

周世傑(Shyh-Jye Jou)

審核日期

2000-7-14

推文