應用於高畫質電視之載波回復電路架構

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姓名

林志鴻(Chih-Hung Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於高畫質電視之載波回復電路架構
(A Sigma-Delta Modulation Based Carrier Recovery Architecture for the ATSC HDTV)

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摘要(中)

在此主要的研究目標是載波回復電路的設計。在許多的數位通訊系統中，載波的同步化是很主要的課題，以一個有效頻寬的調變而言，系統對於相位雜訊是非常敏感的，同時也需要一個非常窄的回路頻寬以得到最小的相位雜訊。不過由於射頻震盪器的不確定性以及通道的影響，造成在系統上接收端最大仍有 100 kHz 的頻率誤差。然而為了維持相位，當有頻率漂移的情況下，載波回復電路仍可以鎖住相位並達到最小的相位雜訊。
由於在 ATSC的規範中多加一個1.25 DC 值的嚮導信號 (Pilot signal) 到資料中，整個調變方式就變成載波傳送 (Transmitted Carrier)。載波傳送的好處在於它可以用比載波壓抑 (Suppressed Carrier) 用更少的硬體來實現同時減少設計的困難度，不過缺點就是要浪費更多的傳送能量。傳統上可以利用 Citta’’s loop 來完成載波同步化。
在提出的新架構中，利用了領先/落後偵測和差值/累加鎖頻迴路等全數位的觀念將它應用在整個系統中來同步化載波訊號。不但整個系統是操作在一階的鎖相迴路之中，沒有不穩定的情況產生。同時只需要一個很簡單的一階 IIR 低通濾波器便可以去除掉大部分的雜訊，使得相位偵測的錯誤機會可以降低到 25%，因此晶片面積更是大幅降低。
我們透過 C 和 Verilog 的模擬驗證其可行性，並且利用 TSMC 0.35μm 製程和CIC 提供的唯讀記憶體來作實現，整個電路只用3000多個邏輯閘(不包括唯讀記憶體)，整個晶片面積為 1000μm X 800μm不但大大減少硬體複雜度並且佈局的面積也很小。同時載波回復電路可將頻率誤差由拉至。在穩定狀態時，最大相位雜訊約是 6 度，相位標準差為 1.5 度。

摘要(英)

In this paper, a carrier recovery circuit for the ATSC HDTV has been proposed and implemented. It uses the Sigma-Delta Modulation to achieve large pull-in range and small steady state variation simultaneously. The proposed architecture has the following distinguishing features. First, it uses only the lead-lag decision for the carrier recovery instead of the phase difference information for the PLL to minimize the hardware complexity. Second, it takes the 1st order PLL approach for the stability and phase jitter considerations. Third, the Sigma-Delta modulation helps achieve large pull-in range and small steady variation. The architecture and the logic design have been verified using C Language and Verilog simulation respectively. The chip has been designed implemented using TSMC 0.35μm technology. The gate count of 3000 reconfirms the simplicity of the architecture.

關鍵字(中)

★ 超大型積體電路
★ 通信積體電路
★ 載波回復電路
★ 嚮導信號
★ 殘邊帶視訊傳輸

關鍵字(英)

★ VLSI
★ Communication IC
★ Carrier Recovery
★ Pilot Signal
★ VSB modulation

論文目次

Chapter Introduction1
1.1Motivation1
1.2ATSC HDTV Transmitter architecture2
1.3VSB modulation and pulse shaping filter 4
1.3.1Weaver Method4
1.3.2Norgard Method6
1.3.3CAP Based Phase Shift Method7
1.3.4Pulse Shaping Filter8
1.4Receiver Blocks9
1.4.1Carrier Recovery10
1.4.2Timing Recovery13
1.5The survey of Delta-Sigma Modulation14
1.6Thesis Organization15
Chapter 216
2.1Introduction16
2.2A first order phase locked loop16
2.3Proposed carrier recovery circuit17
2.3.1A Phase Locked Loop in our proposed CRC 18
2.3.2Frequency loops in proposed CRC25
Chapter 329
3.1Channel Model29
3.2Phase jitter30
3.3Constant Frequency Offset31
3.4Frequency Drift32
3.5Confidence Counter State Change33
3.6IC implementation and Test Consideration34
Chapter 437
Conclusion37

參考文獻

[1] Advanced Television System Committee, ATSC Digital Television Standards, Sept. 1995.
[2] Advanced Television System Committee, Guide to the use of ATSC Digital Television Standards, Oct. 1995.
[3] Wayne Bretl, " VSB Modem Subsystem Design for Grand Alliance Digital Television Receivers", 1995, IEEE
[4] Lim, H, etal., " Low-Complexity Receiver Algorithms for the Grand-Alliance VSB HDTV system, " IEEE Trans. On Consumer Electronic, Vol. 42, No. 3, August 1996, pp640-650.
[5] Sgrignoli, G., W. Bertl, and R. Citta, " VSB Modulation Used for Terrestrial and Cable Broadcasts," IEEE Trans. On Consumer Electronics, Vol. 41, No. 3, Aug. 1995, pp.367-382.
[6] Bertl, W., G. Sgrignoli, G., and P. Snopko, " VSB Modem Subsystem Design for Grand Alliance Digital Television Receivers," IEEE Trans. N Consumer Electronics, Vol. 41, No. 3, Aug. 1995, pp.773-786.
[7] Best, R.E., Phase-Locked Loops-Theory, Design, and Applications 2nd Ed, McGraw-Hill, Inc., New York, U.S.A., 1993
[8] John G. Proakis, Digital Communication, 3nd Ed, McGRAW-HILL INTERNATIONAL EDITIONS
[9] S.C. Yin, C.C. Su, M.T. Shiue, L.Y. Huang, C.K. Wang, S.J. Jou, W.I. Way , " A New VSB Modulation Technique and Shaping Filter Design "IEEE International Symposium on Volume: 4 , 1996 , Page(s): 312 -315 vol.4
[10] Galton, "A practical second-order delta-sigma frequency-to-Digital Converter," Proc. Of 1995 IEEE Int. Symp. Circuits and Systems, Vol.3 of 4, pp.5-8
[11] Galton, William Huff, Paolo Carbone, and Eric Siragusa, "A Delta-sigma PLL for 14-b, 50kSample/s Frequency-to-Digital Conversion of a 10MHZ FM signal," solid-state Circuits, IEEE Journal of Volume: 33 12 , Dec. 1998 , Page(s): 2042 -2053
[12] ROBERT M. GRAY, WU CHOU and PING W. WONG, "Quantization Noise in Sigma-Loop Sigma-Delta Modulation with Sinusoidal Inputs," IEEE TRANSACTIONS ON COMMUNICATIONS. VOL. 37, NO. 9, 1989, p956-968
[13] Ian Galton, "Analog-Input Digital Phase-Locked Loops for Precise Frequency and Phase Demodulation" IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. VOL. 42, NO. 10, OCTOBER 1995, p621-p630
[14] Tom A. D. Riley, Miles A. Copeland, and Tad A. Kwasniewski, "Delta-Sigma Modulation in Fractional-N Frequency Synthesis" IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 28, NO. 5, MAY 1993, p553-p559
[15] JAMES C. CANDY, "A Use of Double Integration in Sigma Delta Modulation" IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. COM-33, NO. 3, MARCH 1985

指導教授

蘇朝琴(Chauchin Su)

審核日期

2000-7-5

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