第二代高速數位用戶迴路中維特比解碼器之FPGA實現

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羅鋒(Feng Lo) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

第二代高速數位用戶迴路中維特比解碼器之FPGA實現
(FPGA Realization of the Viterbi Decoder for HDSL2 Systems)

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摘要(中)

第二代高速數位用戶迴路(HDSL2)被認為是使T1(1.544Mbps)服務更有經濟效率的解決方案。其最大的特點在於利用目前已架構的電話線用戶迴路即可提供T1服務，而且傳輸距離比既有的解決方案還遠。為達此目標，在HDSL2標準中，使用由脈衝振幅調變(PAM)及迴旋碼(convolutional code)所組成格子碼(TCM)為編碼標準。
在本論文中，我們實現了適用於HDSL2系統之迴旋碼編/解碼器。相較於編碼器，解碼器的電路複雜了許多，而且在實際硬體實現時，有許多要素需要列入考慮。在設計的過程中，我們針對實現維特比解碼器(Viterbi decoder)的要素加以探討，並且選定我們所要採用的架構；接著，我們以Matlab程式驗證整個編/解碼運作的過程，並以Verilog硬體描述語言來模擬及驗證電路的正確性。最後，我們以Altera FLEX 10K200E來實現我們的設計。

摘要(英)

In this thesis, we focus on the realization of the convolutional encoder/decoder. The hardware complexity of the decoder is much complicated than the encoder, and there are several implementation issues. In realization, we discuss the implementation issues and a proposed architecture is presented at first. Then, the encoding/decoding process is simulated Matlab program and verified by Verilog HDL. Finally, the encoder/decoder is realized by the FPGA device.

關鍵字(中)

★ 第二代高速數位用戶迴路
★ 迴旋碼
★ 維等比解碼器
★ 維等比演算法

關鍵字(英)

★ HDSL2
★ concolutional code
★ Viterbi Decoder
★ Viterbi Algorithm

論文目次

CHAPTER 1 INTRODUCTION1
1.1THE HDSL2 SYSTEM1
1.2MOTIVATION AND OBJECTIVE4
1.3THESIS ORGANIZATION6
CHAPTER 2 CONVOLUTIONAL CODES AND THE VITERBI ALGORITHM7
2.1CONVOLUTIONAL CODES8
2.2THE CONVOLUTIONAL ENCODER IN HDSL2 SYSTEMS14
2.3THE VITERBI ALGORITHM17
CHAPTER 3 IMPLEMENTATION ISSUES OF VITERBI DECODERS25
3.1METRICS NORMALIZATION SCHEMES25
3.2SURVIVOR MEMORY MANAGEMENT IN VITERBI DECODERS30
3.3ACSU SHARING42
3.4ARCHITECTURES FOR THE PROPOSED VITERBI DECODER46
CHAPTER 4 FPGA REALIZATION49
4.1INTRODUCTION TO FPGAS49
4.2ALTERA FLEX 10K200E51
4.3FPGA DESIGN FLOW54
4.4MATLAB SIMULATION RESULTS56
4.5REALIZATION60
CHAPTER 5 CONCLUSION71
5.1FUTURE WORKS71
REFERENCE73
APPENDIX75

參考文獻

[1] Http://www.hdsl2.org
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[3] Draft for HDSL2 Standard, Letter Ballot, ANSI T1E1.4, June 1999.
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[11] Andries P. Hekstra, "An alternative to metric rescaling in Viterbi decoders," IEEE Trans. on Commu., vol. COM-37, no. 11, pp. 1220-1222, Nov. 1989.
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[13] Ivan M. Onyszchuk, "Truncation Length for Viterbi Decoding," IEEE trans. Commu., vol. COM-39, pp. 1023-1026, July 1991.
[14] P. J. Black and T. H. Y. Meng, "Hybrid Survivor Path Architecture for Viterbi Decoders," in Proc. ICASSP 93, 1993, pp. I-433-I-436.
[15] J. Sparso, H. J. Jorgensen, E. Paaske, S. Pedersen and T. R. Petersen, " An Area-Efficient Topology for VLSI Implementation of Viterbi Decoders and Other Shuffle-Exchange Type structures," IEEE Journal of Solid-State Circuits, vol. 26, no. 2, Feb. 1991.
[16] M. Boo, F. Arguello, J. D. Bruguera, R. Doallo and E. L. Zapata, "High-Performance VLSI Architecture for the Viterbi Algorithm," IEEE Trans. Commu., Vol. 45, no. 2, Feb. 1997.
[17] M. D Ciletti, Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL, Prentice-Hall Inc., New Jersey, 1999
[18] Altera Digital Library, Altera Inc., Jan. 2000

指導教授

吳安宇(An-Yeu Wu)

審核日期

2000-7-17

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