參考文獻 |
[1] C. A. Mead:"Schottky Barrier Gate Field Effect Transistor," Proc. IEEE, 54, pp.307-308(1966)
[2] K. Drangeid, R. Sommerhalcler and W. Walter: "High-speed gallium arsenide Schottky-barrier field effect transistors," Electron, Lett., Vot. 6, pp.228-229, April 1970
[3] For a discussion on ion implantation in silicon, see, for example. T. E. Seidel, "Ion Implantation," in S. M. Sze, Ed., VLSI Technology, McGraw-Hill, New York, 1983.
[4] I. Brodie and J. J. Muray, The Physics of Microfabrication, Plenum, New York, 1982.
[5] S. M. Sze, "Semiconductor Devices: Physics and Technology," Chap. 10, John Wiley & Sons, 1985.
[6] M. T. Robinson, and O. S. Oen, Applied Physics Letter, vil. 2, pp. 30, 1963.
[7] R. A. Moline, J. Applied Physics, vol. 42, pp. 3553, 1973.
[8] R. G. Wilson, J. Applied Physics, vol.52, pp. 3985, 1985.
[9] K. Yamazaki, N. Kato, and M. Hirayama, "Below 10ps/Gate Operation with Buried P-Layer SAINT FETs," Electronics Letters, Vol. 20, Nos. 25/26, p.1029, 1984.
[10] K. Yamazaki, N. Kato, and M. Hirayama, "Buried P-Layer for Very High Speed GaAs LSI's with Submicrometer Gate Length," IEEE Transactions on Electron Device, Vol. ED-32, No. 11, p.2430, 1985.
[11] K. L. Tan, H. K. Chung, and C. H. Chen, "Improvement in Threshold Implanted P Layer," IEEE Electron Device Letters, Vol. EDL-8, No. 9, p.440, 1987.
[12] Y. Umemoto, S. Takahashi, N. Matsunaga, and M. Nakamura, "GaAs MESFETs with A Buried P-Layer for Large Scale Integration," Electronics Letters, Vol. 20, No. 2, p.98, 1984.
[13] K. L. Tan, H. K. Chung, B. L. Grung, and S. M. Shin, "A Submicron Self-Align Gate MESFET Technology for Low Power Subnanosecond Static RAM Fabrication," IEEE GaAs IC Symposium, p.121, 1987.
[14] N. Matsunaga, M. Miyazaki, Y. Umemoto, J. Shigeta, H. Tanaka, and H. Yanazawa, "Gallium Arsenide MESFET Technologies with 0.7mm Gate-Length for 4kb 1ns Static RAM," IEEE GaAs IC Symposium, p.129, 1987.
[15] P. C. Canfield and L. Forbes, "Buried Channel GaAs MESFET's with Frequency-Independent Output Conductance," IEEE Electron Device Letters, Vol. EDL-8, p.88, 1987.
[16] J. M. Pate, et al., Surface Modification and Alloying, Plenum, 1983, p.133.
[17] Y. Shioya and M. Maeda, J. of Applied Physics, Vol. 60, 1986, p.327.
[18] D. Pramanik, et al., Semiconductor International, May 1985.
[19] S. Prussin, et al., J. Applied Physics, Vol. 57, 1985, p.180.
[20] S. Wolf, Silicon Processing for the VLSI Era, Vol. 1, Ch. 9, Lattice Press, 1986.
[21] S. R. Wilson, Solid State Technology, June 1985, p.185.
[22] S. J. Lee and C. R. Crowell, "Parasitic source and drain resistance in high-electron-mobility transistor," Solid-state Electron, Vol. 28, p.659-668, 1985.
[23] Dieter K. Schroder, Semiconductor Material and Device Characterization, Wiley-Interscience, 1990.
[24] N. Braslau, "Alloyed Ohmic Contact to GaAs," Journal of Vaccum Science & Technology B, Vol. 19, No. 3, 1981.
[25] M. Heiblum, M. I. Nathan, and C. A. Chang, "Characteristics of AuGeNi Ohmic Contact to GaAs," Solid State Electronics, Vol. 11, No. 6, p.2505, 1993.
[26] R. T. Tung, "Electron Transport of Inhomongeneous Schottky Barrier," Appl. Phys. Lett. 58, 2821-2823, 1991.
[27] C. R. Crowell, J. C. Sarace and S. M. Sze, "Tungsten-Semiconductor Schottky-Barrier Diodes," Trans. Met Soc. AIME, 233, 478, 1965.
[28] G. Gonzalez, "Microwave Transistor Amplifier Analysis and Design, " Prentice-hell, 1984.
[29] B. E. Maile, "Fabrication Limits of Nanometer T and G Gates: Theory and Experiment," Journal Vaccum Science and Technology B, Vol. 11, No. 6, p.2502, 1993. |