博碩士論文 108521058 詳細資訊




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姓名 張家睿(Jia-Ruei Chang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 DITM模型上不同測試方法和測試流程的良率分析
(Yield Analysis of Different Test Method and Test Flow on DITM Model)
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摘要(中) 本論文以DITM(digital integrated-circuit testing model)測試模型為基礎,並以自動規劃測試防護帶的測試系統(auto-guardbanding)為輔助,在假設相同的缺陷程度(Defect Level)的前提下,比較不同重複測試方案和不同測試流程對測試良率的影響。
首先,使用一種以統計概念開發的DITM測試模型,並以測試良率與測試品質做為測試結果的評斷標準。此模型以常態分佈為基礎,納入多項表達製造能力與測試能力的參數,並輔以測試防護帶與重複測試的概念,衍伸出一套嶄新的測試機制。
接著,透過簡化重複測試公式,以及比較測試規格(TS)-測試品質(Test Quality)圖的關係,決定使用二分法(bisection method)來實現自動規劃測試防護帶的測試系統(auto-guardbanding),其能在固定測試品質與次數的條件下,迅速得出適當的測試規格。
最終透過上述的測試模型以及測試系統的輔助,先比較不同的重複測試方案,再比較不同的重測(retest)測試流程對測試良率的影響。
摘要(英) This paper is based on the DITM test model, and is assisted by an auto-guardbanding test system. Under the premise of assuming the same Defect Level, compare the impact of different repeat test schemes and different testing processes on the test yield.
First, a DITM test model developed with statistical concepts is used, and the test yield and test quality are used as the evaluation criteria for test results. This model is based on the normal distribution, incorporates a number of parameters that express the manufacturing capability and testing capability, and is supplemented by the concepts of testing guard bands and repeated testing, and a new testing mechanism is derived.
Then, by simplifying the repeat test formula and comparing the relationship between the test specification and the test quality diagram, it is decided to use the bisection method to realize the auto-guardbanding test system that automatically plans the test guardband. It can quickly obtain appropriate test specifications under the condition of fixed test quality and frequency.
Finally, with the aid of the above-mentioned test model and test system, firstly compare different repeat test schemes, and then compare the impact of different retest test procedures on the test yield.
關鍵字(中) ★ 重複測試
★ 重測
★ 自動測試防護帶規劃
關鍵字(英) ★ repeat test
★ retest
★ auto guardband
論文目次 摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 v
表目錄 vii
第一章 緒論 1
第二章 預備知識 4
2.1 常態分布 4
2.2. 製造良率估算 4
2.3 臨界比較式測試 6
2.4 測試良率估算 6
2.5 測試品質評估 6
第三章 重複測試之測試防護帶自動規劃 8
3.1 測試防護帶 8
3.2 重複測試 9
3.3 重複測試公式的簡化 13
3.3.1 各次測試的獨立性 14
3.3.2 測試良率公式之簡化 15
3.3.3 測試良率公式之遞迴化 18
3.4 使用二分法來實現測試防護帶自動規劃 18
第四章 測試方案與流程對測試良率影響之比較 21
4.1 不同測試方案之比較 21
4.2 不同測試流程之比較 32
第五章 結論 41
參考文獻 42
參考文獻 [1] International Technology Roadmap for Semiconductors, Test and Test Equipment. 2001. http://www.itrs2.net/itrs-reports.html 2001, 5-6.
[2] International Technology Roadmap for Semiconductors 2.0., System Integration. 2015. http://www.itrs2.net/itrs-reports.html 2015 , 7-13.
[3] R. J. Montoya, “Using Tester Repeatability to Improve Yields”, In Proceedings of International Test Conference, pp. 270-274, Washington, DC, USA, Sep. 1992.
[4] S. C. Horng et al. 2003. “Reducing the overkills and retests in wafer testing process,” In Proceeding of Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI, Munich, Germany, WCECS 2011. San Francisco, USA, 1058-1063.
[5] C. -H. Yeh and J. -E. Chen, “Multiple Tests for Maximizing the Yield without Degrading Quality,” in Proc. of the 3rd VLSI Test Technology Workshop, pp.76-81, Taiwan, 2009.
[6] J. -E. Chen and C. -H. Yeh, “Test Guardbanding for Yield and Quality Estimation,” in Proc. of the. International Test Synthesis Workshop, pp. 114-115、USA, 2004.
[7] C. L. Henderson, R. H. Williams, and C. F. Hawkins, “Economic Impact of Type I Test Errors at System and Board Levels,” in Proc. of the International Test Conference (ITC), pp. 441-451, Baltimore, MD、USA, 1992.
[8] 黃則家, “Achievement of Auto Guard-banding in High-Quality Repeat Test”, 碩士論文, 中央大學, 2022.
[9] C. -H. Yeh and J. -E. Chen, “Using Enhanced Test Systems Based on Digital IC Test Model for the Improvement of Test Yield
” Journal of Electronic Testing, Vol 11, 7,2022.
[10] Chang, P.; Huang. Intelligent Method for Retesting a Wafer. Teslence Technology Co., Ltd. Retrieved Apirl 3, 2021 from https://www.swtest.org/swtw_library/2019proc/PDF/S02_02_Chang_SWTest_2019.pdf
[11] Shin-Yeu Lin and Shih-Cheng Horng, “Application of an Ordinal Optimization Algorithm to the Wafer Testing Process”, IEEE Transactions on Systems, Man, and Cybernetics - Part A: Systems and Humans
, Vol 36, 6, pp. 1229-1234, NOVEMBER 2006
[12] West. B. G. 1999, “Accuracy requirements in at-speed functional test,” International Test Conference 1999, Proceedings (IEEE Cat. No.99CH37034).AtlanticCity, NJ, USA, 780-787, https://doi.org/10.1106/TEST.1999.805808.
[13]C. -H. Yeh and J. -E. Chen, “Repeated Testing Applications for Improving the IC Test Quality to Achieve Zero Defect Product Requirements,” Journal of Electronic Testing, Vol 35, 4, pp. 459–472, 2019.
指導教授 陳竹一(Jwu-e Chen) 審核日期 2022-8-1
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