使用次諧波注入鎖定四相位鎖頻迴路暨反串接二極體之毫米波高性能正交調變器研製

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姓名

林天義(Tien-Yi Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

使用次諧波注入鎖定四相位鎖頻迴路暨反串接二極體之毫米波高性能正交調變器研製
(Research on Millimeter-Wave High-Performance Quadrature Modulator Using Sub-Harmonic Injection-Locked Quadrature Frequency-Locked Loop and Anti-Series Diode Technique)

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至系統瀏覽論文 (2027-7-31以後開放)

摘要(中)

本論文主要針對毫米波頻段次諧波注入鎖定鎖頻迴路整合正交調變器與提出高性能反串接二極體架構BPSK與正交反射式調變器研製。第二章是Ka頻段次諧波注入鎖定四相位壓控振盪器(SILQVCO)，使用疊接交錯耦合振盪核心克服製程最高頻率的限制，並利用正交注入鎖定技術降低振盪器的相位雜訊和正交誤差。使用台積電0.18 μm CMOS製程技術實現，最高操作頻率為27.9 GHz，可調頻率範圍為從26.2至27.9 GHz (6.4%)，最大輸出功率為-13 dBm，自由振盪頻率下距載波偏移1 MHz最佳相位雜訊為-91.7 dBc/Hz，注入鎖定後距載波偏移1 MHz最佳相位雜訊為-122.2 dBc/Hz，整體電路優化指標FoMPN為-195.2。此外，正交輸出相位誤差與振幅誤差分別為1.05˚與0.21 dB，核心直流功耗不含緩衝放大器為36.6 mW，晶片面積為1.005×1.155 mm2。
第三章是Ka頻段具低相位雜訊低抖動次諧波注入鎖定鎖頻迴路(SILFLL)整合正交相位調變器(IQ modulator)，該電路使用疊接交錯耦合技術提升最高操作頻率，並且使用正交注入鎖定技術進一步降低振盪器的相位雜訊和正交誤差。使用台積電0.18 μm CMOS製程技術實現，該電路量測最高頻率為28.2 GHz。使用次諧波注入鎖定技術能使毫米波操作頻率下擁有較低抖動，量測最低方均根抖動量可到46.9 fs。而頻率追蹤迴路技術可自適應調整控制電壓能抵抗電壓溫度與製程變異，使得鎖頻迴路穩定運作從26.5至28.2 GHz，注入鎖定輸出頻率範圍為1.7 GHz (6.2%)，最大輸出功率為-12.2 dBm，注入鎖定後距載波偏移1 MHz最佳相位雜訊為-122 dBc/Hz，整體電路優化指標FoMPN為-195。所推薦的反射式調變器具有低輸入損耗、低直流功耗與低電路複雜度的特色。量測旁波抑制量為-30.5 dBc，LO抑制量為-24.3 dBc，複雜數位調變可達64-QAM調變方案。在1 Mbps符元率的傳輸下，量測星座圖顯示出對稱整齊，誤差向量振幅(EVM)為2.75%，電路總體直流功耗為62 mW，晶片面積為1.23×1.46 mm2。
第四章是提出毫米波頻段反串接架構的反射式調變器，實現電路包含傳統架構BPSK調變器、反串接BPSK調變器架構、傳統架構正交調變器與反串接架構正交調變器。此章節總共四顆電路並且以穩懋半導體股份有限公司所生產製造的砷化鎵(GaAs) PIN二極體製程技術實現。由反射式調變器基礎理論，利用數學方程針對所提出電路架構進行分析與驗證。由穿透係數對二極體偏壓進行高階微分數學分析結果，可知所提出反串接架構具有較小的高階互調失真和較優異的線性度。高次項互調抑制量測結果亦和理論結果吻合，相較於傳統架構調變器，反串接二極體架構展現高線性度、高互調抑制量且具備高階星座圖調變方案。對於傳統架構二進制調變器，在1 Mbps符元率傳輸下，量測誤差向量振幅(EVM)為1.22%。所提出反串接架構二進制調變器，在1 Mbps符元率傳輸下，量測誤差向量振幅(EVM)為0.37%。對於傳統反射式正交調變器，在1 Mbps符元率傳輸和64-QAM調變下，量測誤差向量振幅(EVM)為3.37%。使用IEEE 802.11a無線規格，在54 Mbps位元率傳輸和正交頻率區分多工(OFDM) 64-QAM調變下，量測誤差向量振幅(EVM)為-22.5 dB。所提出反串接架構二進制調變器，在1 Mbps位元率傳輸和256-QAM調變下，量測誤差向量振幅(EVM)為1.18%，量測結果呈現256-QAM清晰星座圖。在54 Mbps位元率傳輸和正交頻率區分多工(OFDM) 64-QAM調變下，量測誤差向量振幅(EVM)為-31.3 dB。

摘要(英)

The thesis presented a few high-performance IQ modulators for high-speed and millimeter-wave (mm-wave) applications. An I/Q modulator integrated with a sub-harmonic injection-locked frequency-locked loop and high-performance anti-series BPSK and quadrature reflection-type modulators are proposed using some advance CMOS and GaAs processes. A Ka-Band sub-harmonic injection-locked quadrature voltage-controlled oscillator (SILQVCO) is presented in Chapter 2 using TSMC 0.18 μm CMOS process. A stack-boosting technique is employed in the cross-coupled core to further enhance the negative resistance and overcome the limitation of the CMOS process. In addition, a quadrature dual-injection technique is used to reduce the phase noise and the quadrature error. The maximum operation frequency of the proposed SILQVCO is up to 27.9 GHz. The tuning range is from 26.2 to 27.9 GHz with a fractional bandwidth of 6.4%. The highest output power is -13 dBm. Under the free-running condition, the measured lowest phase noise at 1-MHz offset frequency is -91.7 dBc/Hz. Under the injection-locked condition, the measured lowest phase noise at 1-MHz offset frequency is -122.5 dBc/Hz with a state-of-the-art figure-of-merit (FoMPN) of -195.2. Moreover, the measured phase error and amplitude error are 1.05˚ and 0.21 dB, respectively. The core DC power consumption without the buffers is 36.55 mW. The chip size, including RF and DC pads, is 1.005×1.155 mm2.
In Chapter 3, a Ka-Band low-phase noise and low-jitter sub-harmonic injection-locked frequency-locked loop (SILFLL) IQ modulator is proposed using TSMC 0.18 μm CMOS process. The stack-boosting and quadrature dual-injection techniques are both adopted to enhance the maximum frequency and reduce phase noise and the quadrature error. The measured highest frequency of the proposed circuit is up to 28.2 GHz. The measured lowest rms jitter is 46.9 fs. As can be observed, the frequency-tracking loop (FTL) can be employed to adaptively tuning the controlled voltage to resist the process, voltage, and temperature variations, and the measured SILFLL frequency is from 26.5 to 28.2 GHz. The measured output injection-locked frequency range is 1.7 GHz with a fractional bandwidth of 6.2%. The measured highest output power is -12.2 dBm. Under the injection-locked condition, the measured lowest phase noise at 1-MHz offset frequency is -122 dBc/Hz with a lowest FoMPN of -195. The proposed injection-locked quadrature modulator features low insertion loss, low dc power consumption, and low circuit complexity. The measured single sideband and LO suppressions are better than -30.5 and -24.3 dBc, respectively. The digital modulation scheme is successfully performed up to 64-QAM with a 1-Mbps symbol rate. The measured lowest error vector magnitude (EVM) of the 64-QAM modulation is 2.75%. The DC power consumption is 62 mW. The chip size, including RF and DC pads, is 1.23×1.46 mm2.
In Chapter 4, several mm-wave conventional modified and proposed anti-series diode reflection-type modulators, including the conventional modified reflection-type and anti-series diode BPSK modulators, the conventional modified reflection-type and anti-series diode IQ modulators, are presented using GaAs PIN diode process provided by WIN Semiconductors Corporation. The principle of the reflection-type modulator is introduced, and the mathematical models of the conventional modified reflection-type and the proposed modulators are presented to verify the linearity of the modulators. The high-order derivations of the transmission coefficients versus diode bias for the modulators are presented to evaluate the intermodulation distortion of the conventional modified reflection-type and the proposed anti-series diode modulators. The measured results of the high-order intermodulation suppressions show good agreement with the theoretical results. As compared with the conventional modulator, the proposed anti-series diode modulator exhibits high linearity and good intermodulation suppression, and also it is suitable for high-level modulation schemes. As the symbol rate is 1 Mbps, the measured EVMs of the BPSK modulation for the conventional and the proposed BPSK modulators are 1.22% and 0.37%, respectively. As the symbol rate is 1 Mbps with 64-QAM modulation, the measured EVM of the conventional IQ modulators is 3.37%. As the symbol rate is 1 Mbps with 256-QAM modulation, the measured EVMs of the proposed IQ modulators are 1.18%, respectively. Under the IEEE 802.11a wireless communication standard with a bit rate of 54 Mbps, the measured EVMs of 64-QAM orthogonal frequency division multiplexing (OFDM) modulation for the conventional and the proposed IQ modulators are -22.5 and -31.25 dB, respectively.

關鍵字(中)

★ Ka頻段
★ 鎖頻迴路
★ 四相位
★ 正交調變器
★ 振盪器
★ 次諧波注入鎖定

關鍵字(英)

★ Ka-band
★ Frequency-locked loop
★ Quadrature
★ I/Q modulator
★ Oscillator
★ Sub-harmonically injection-locked

論文目次

摘要 I
Abstract III
目錄 VI
圖目錄 IX
表目錄 XIX
第一章緒論 1
1.1 研究動機及背景 1
1.2 相關研究發展 2
1.3 論文貢獻 3
1.4 論文架構 4
第二章 Ka頻段變壓器耦合式次諧波注入鎖定四相位壓控振盪器 5
2.1 簡介 5
2.2 注入鎖定原理與頻率倍頻器介紹 6
2.2.1 注入鎖定原理概述[28] 6
2.2.2 頻率倍頻器介紹 9
2.3 電路設計及分析 11
2.3.1 變壓器設計[49] 14
2.3.2 疊接增強負阻分析 15
2.4 電路實現及實驗結果與討論 17
2.4.1 次諧波注入鎖定四相位振盪器頻率及鎖定範圍量測 18
2.4.2 次諧波注入鎖定四相位振盪器頻率偏移及誤差除錯 25
2.5 總結 28
第三章應用疊接增強技術之Ka頻段高線性度注入鎖頻迴路整合正交調變器 30
3.1 簡介 30
3.2 次諧波注入鎖定鎖頻迴路(SILFLL)系統模擬 31
3.2.1 波德圖穩定度模擬與分析 33
3.2.2 閉迴路暫態分析 35
3.2.3 次諧波注入鎖定鎖頻迴路(SILQFLL)相位雜訊分析[49] 36
3.3 電路設計及分析 37
3.3.1 次諧波注入鎖定四相位壓控疊接振盪器[50] 38
3.3.2 類比式低功耗高速頻率比較器[30] 40
3.3.3 電壓轉電流放大器 43
3.3.4 反射式正交調變器 45
3.4 SILQFLL電路實現及實驗結果與討論 50
3.4.1 次諧波注入鎖定四相位壓控振盪器量測 52
3.4.2 鎖頻迴路量測 57
3.4.3 正交調變器量測 61
3.5 總結 68
第四章高線性度Ka頻段二進制相位及正交調變器 70
4.1 簡介 70
4.2 二進制相位調變器[65] 71
4.2.1 傳統與反串接架構設計與分析 71
4.2.2 調變線性度分析 79
4.2.3 S參數量測結果 93
4.2.4 EVM量測結果 100
4.3 正交相位調變器 109
4.3.1 傳統與反串接架構設計及分析 109
4.3.2 S參數量測結果 116
4.3.3 旁波抑制量測結果 125
4.3.4 EVM量測結果 128
4.4 總結 139
第五章結論 142
參考文獻 144

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指導教授

張鴻埜(Hong-Yeh Chang)

審核日期

2022-8-11

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