具單一自適應系統之低功耗16 Gbps連續時間線性等化器與四分之一速率決策回授等化器

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：111

、訪客IP：3.133.111.183

姓名

張鈞堯(Chun-Yao Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具單一自適應系統之低功耗16 Gbps連續時間線性等化器與四分之一速率決策回授等化器
(A Low Power 16 Gbps CTLE and Quarter-Rate DFE With Single Adaptive System)

相關論文

★ 一種應用於觸控液晶顯示器的新型嵌入式開關	★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計	★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路	★ 全數位任意責任週期之同步映射延遲電路
★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測	★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統
★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路	★ 高解析度可變動責任週期之同步複製延遲電路
★ 奈米CMOS晶片內序列傳輸之接收器	★ 奈米CMOS晶片內序列傳輸之送器
★ 基於鎖相迴路之多重相位脈波產生器	★ 低能量時脈儲存元件之分析、設計與量測
★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器	★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 (2028-5-31以後開放)

摘要(中)

近年來資料傳輸的需求大幅上升，高速串列傳輸介面也陸續推出更高傳輸速率的規格以符合市場需求。傳輸速率逐漸提升的同時，資料經過傳輸通道而受到符碼間干擾越來越嚴重，因而必須使用等化器對資料進行補償以優化接收資料的訊號品質。過去文獻提出各式各樣的等化器架構與電路因應日益增加的傳輸速率，卻因此消耗大量功率或面積，使得串列傳輸系統的能源效率越來越差。與其一味的追求高資料速率的傳輸介面，不如發展能應用在高資料速率上的低功耗技術。
本論文提出一個新架構的等化器，由連續時間線性等化器以及決策回授等化器構成，藉由新的補償方法讓決策回授等化器的時間限制從一個資料位元週期，拓寬為兩個資料位元週期。解放了決策回授等化器的時間限制使得其能使用低功耗電路實現，同時操作於高資料速率。此外，本論文使用自適應系統收斂兩等化器權重，以達到正確的補償量。本論文基於新架構的等化器提出一新的自適應收斂方法，能使用單一自適應機制同時收斂兩等化器的權重。
本論文使用TSMC 90 nm (TN90GUTM) 1P9M CMOS 製程實現，電路操作電壓為1.0 V，在佈局後模擬的最大輸入資料速率為16 Gbps，輸入時脈頻率為8 GHz，通道衰減為16 dB。核心電路整體功率消耗為5.40 mW，其中連續時間線性等化器為1.78 mW，決策回授等化器為1.12 mW，自適應機制為2.50 mW。量測時最大輸入資料速率為8 Gbps，輸入時脈頻率為4 GHz，通道衰減為21 dB。核心電路整體功率消耗為4.3 mW，其中連續時間線性等化器為1.8 mW，決策回授等化器為0.6 mW，自適應機制為1.9 mW。晶片面積為1.2 mm2，其中核心電路面積為0.047 mm2。

摘要(英)

In recent years, as the demand of data communication has increased rapidly, high speed serial link interface come out with new specification operating at higher data rate to be in line with the market’s demand. While the data rate increases gradually, the channel bandwidth does not follow up. Since then, the data suffers more inter-symbol-interference (ISI), it is necessary to use equalizer compensate the data for ensuring the quality of received signal. The past assay proposed various types of equalizer to deal with the increasing data rate. However, these methods make the energy efficiency of high-speed serial link system worse. Therefore, we should research for low power techniques rather than high data rate interface.
This thesis proposes a new architecture of equalizer, which is composed by continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE). It broadens the time constrain of DFE from one data period to two data period by new compensation method. Since we broaden the time constrain of DFE, we are able to use low power techniques on equalizer. Moreover, this thesis uses adaptive system to converge the weight of both equalizers to obtain correct compensation. This thesis proposes a new adaptive method based on the proposed equalizer, and this allow us to converge boost gain of CTLE and the tap weighting of DFE at the same time with single adaptive system.
The fabricated chip was implemented by TSMC 90 nm (TN90GUTM) 1P9M CMOS process. In post-layout simulation, power supply is 1.0 V, the input data rate is 16 Gbps, the input clock frequency is 8 GHz, and the channel loss is 16 dB. The power consumption of core is 5.40 mW, which includes CTLE consumed 1.78 mW, DFE consumed 1.12 mW, and adaptive system consumed 2.50 mW. In measurement results, the input data rate is 8 Gbps, the input clock frequency is 4 GHz, and the channel loss is 21 dB. The power consumption of core is 4.3 mW, which includes CTLE consumed 1.8 mW, DFE consumed 0.6 mW, and the adaptive system consumed 1.9 mW. The chip area is 1.2 mm2 and the core area is 0.047 mm2.

關鍵字(中)

★ 自適應等化器
★ 連續時間線性等化器
★ 決策回授等化器

關鍵字(英)

★ Adaptive Equalizer
★ Continuous-Time Linear Equalizer (CTLE)
★ Decision Feedback Equalizer (DFE)

論文目次

摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 vii
表目錄 xi
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 4
第2章高速串列傳輸之訊號完整性分析 5
2.1 隨機二位元資料 5
2.1.1 隨機二位元資料特性 5
2.2 傳輸線理論 6
2.2.2 傳輸線模型 6
2.2.2 傳輸線損失 10
2.3 抖動分析 14
2.3.1 隨機抖動(Random Jitter, RJ) 14
2.3.2 定量性抖動(Deterministic Jitter, DJ) 15
2.3.2.1 週期性抖動(Period Jitter, PJ) 15
2.3.2.2 責任週期失真(Duty Cycle Distortion, DCD) 16
2.3.2.3 資料相關抖動(Data Dependent Jitter, DDJ) 16
2.4 單一位元脈衝響應與等化器之關係 17
2.5 眼圖分析 19
2.6 誤碼率 20
第3章等化器與自適應機制之簡介 23
3.1 連續時間線性等化器(CTLE) 23
3.1.1傳統連續時間線性等化器 23
3.1.2具電感之連續時間線性等化器 25
3.2 決策回授等化器(DFE) 26
3.2.1 離散時間決策回授等化器(DT-DFE) 27
3.2.2 無限脈衝響應決策回授等化器(IIR-DFE) 30
3.2.3 離散時間/無限脈衝響應決策回授等化器(DT/IIR-DFE) 31
3.2.4 全速率決策回授等化器(Full Rate DFE) 32
3.2.5 半速率決策回授等化器(Half Rate DFE) 32
3.2.6 四分之一速率決策回授等化器(Quarter Rate DFE) 33
3.3 前饋式等化器(FFE) 34
3.4 自適應機制 35
3.4.1 頻譜平衡技術(Spectrum Balancing Technique) 35
3.4.2 最小均方演算法(Least Mean Square Algorithm) 36
3.4.2.1 SS-LMS之實現 39
3.4.2.2 SS-LMS之使用限制 39
3.4.3 逼零演算法(Zero-Forcing Algorithm) 41
3.5 比較與討論 42
第4章等化器與自適應系統的電路架構與相關模擬 43
4.1 設計流程 43
4.2電路架構 44
4.3 系統分析 45
4.3.1 等化器補償之分析 45
4.3.2 自適應機制之分析 47
4.4 行為模擬 48
4.5 電路介紹 50
4.5.1 連續時間線性等化器(CTLE) 50
4.5.2 二階決策回授等化器(2-Tap DFE) 50
4.5.3 自適應演算法(Adaptive Algorithm) 57
4.5.3.1 LMS演算系統(LMS Algorithm System) 58
4.5.3.2 增益控制系統(Gain Control System) 60
4.5.3.3 自動鎖定電路(Auto Lock System) 62
4.5.4 時脈電路(Clocking Circuit) 63
4.5.4.1 四相位除頻器 63
4.5.4.2 除頻器 64
4.6 模擬結果 65
4.6.1 通道模型 65
4.6.2 佈局前模擬 67
4.6.3 佈局後模擬 70
4.6.4 模擬結果整理與分析 73
第5章晶片佈局與量測 78
5.1 晶片佈局 78
5.1.1 晶片封裝配置 79
5.1.2 佈局規劃與電源配置 81
5.2 量測考量 82
5.2.1 量測環境 82
5.2.2 高速輸入緩衝器 83
5.2.3 高速輸出緩衝器 84
5.2.4 M8048A ISI通道 86
5.3 晶片與印刷電路板照相 88
5.4 量測結果 89
5.4.1 四相位除頻器量測 89
5.4.2 具自適應等化器之量測 92
5.4.3本論文量測之問題與分析 96
5.5 規格比較表 99
第6章結論 101
6.1 結論 101
6.2 未來研究方向 101
參考文獻 104

參考文獻

[1] VESA DisplayPort Standard, Version 2.0, Jun. 2019.
[2] Universal Serial Bus 4 Specification, Version 1.0, May 2021.
[3] Serial ATA Specification, Revision 3.5a, SATA-IO, Mar. 2021.
[4] PCI Express Base Specification, Revision 6.0, Version 1.0, PCI-SIG, Jan. 2022.
[5] 孫世洋, “以符碼間干擾偵測技術實現自適應等化器之5 Gbps半速率時脈與資料回復電路,” 碩士論文, 國立中央大學, 2016.
[6] Behzad Razavi, Design of Integrated Circuits for Optical Communications. McGraw-Hill: Behzad Razavi, 2003.
[7] A. X. Widmer, and P. A. Franaszek,”A DC-balanced, partitioned-block, 8b/10b reansmission code,” IBM J. Res and Develop., vol. 27, pp. 440-451, Sep. 1983.
[8] F. T. Ulaby and U. Ravaioli, Transmission Lines, in Fundamentals of Applied Electromagnetics, 6th ed. United Kingdom: Pearson, 2015, ch. 2, pp. 62-134.
[9] S. H. Hall, G. W. Hall, and J. A. McCall, High-speed digital system design-Ahandbook of interconnect theory and design practices, John-Wiley, 1st ed., 2002
[10] J. C. Rautio and V. Demir, "Microstrip conductor loss models for electromagnetic analysis," in IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 3, pp. 915-921, March 2003.
[11] 吳瑞北.(2019) Electric Properties of Dielectrics [PDF].Available: http://cc.ee.ntu.edu.tw/~rbwu/rapid_content/course/highspeed/SI6_Dielectric.pdf.
[12] Tektronix, “數位示波器的應用抖動(jitter)測量”.
[13] R. Sarpeshkar, T. Delbruck and C. A. Mead, “White noise in MOS transistors and resistors,” IEEE Circuits and Devices Magazine, vol. 9, no. 6, pp. 23-29, Nov. 1993.Agilent Technologies, “Finding sources of jitter with real-time jitter analysis,” 2008.
[14] Agilent Technologies, “Jitter Fundamentals: Agilent 81250 ParBERT Jitter Injection and Analysis Capabilities,” Application Note: 5988-9756EN, July 17, 2003.
[15] Agilent Technologies, “Finding sources of jitter with real-time jitter analysis,” 2008.
[16] N. Na, D. M. Dreps and J. A. Hejase, “DC wander effect of DC blocking capacitors on PCIe Gen3 signal integrity,” in Proc. IEEE 63rd Electronic Components and Technology Conference, May 2013, pp. 2063-2068.
[17] 黃清和, 具可補償19-40 dB 通道衰減之20 Gbps 接收端自適應等化器,” 碩士論文, 國立中央大學, 2022.
[18] Altera Corporation, “Deterministic Jitter (DJ) Definition and Measurement,” 2009.
[19] Maxim, “Optical receiver performance evaluation”.
[20] J.-S Choi, M.-S Hwang, and D.-K. Jeong, “A 0.18-µm CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method,” IEEE J.Solid-State Circuits, vol. 39, no. 3, pp.419-425, Mar. 2004.
[21] C. A. Belfiore and J. John H. Park, “Decision Feedback Equalization,” Proceedings of the IEEE, vol. 67, pp. 1143-1156, Aug. 1979.
[22] A. Agrawal, J. Bulzacchelli, T. Dickson, Y. Liu, J. Tierno and D. Friedman, “A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 3220–3231, Dec. 2012.
[23] J. Lee, "A 20-Gb/s Adaptive Equalizer in 0.13-µm CMOS Technology," in IEEE Journal of Solid-State Circuits, vol. 41, no. 9, pp. 2058-2066, Sept. 2006.
[24] K. -H. Cheng, Y. -C. Tsai, Y. -H. Wu and Y. -F. Lin, "A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 5, pp. 324-328, May 2010.
[25] J. F. Bulzacchelli et al., "A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology," in IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 3232-3248, Dec. 2012.
[26] B. Kim et al., "A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS", IEEE J. Solid-State Circuits, vol. 44, pp. 3526-3538, Dec. 2009.
[27] 陳紫宜, “具高通濾波補償之10 Gb/s 全速率自適應四階脈波振幅調變等化器,” 碩士論文, 國立中央大學, 2019.
[28] S. Haykin, “Wiener Filters,” in Adaptive Filter Theory, 5th ed., United Kingdom: Pearson, 2012, ch. 2, pp. 90-122.
[29] 陳俊諺, “以逼零演算法實現無外部校正之單一自適應系統之5 Gbps 全速率連續時間線性等化器與決策回授等化器,” 碩士論文, 國立中央大學, 2018.
[30] T. O. Dickson, J. F. Bulzacchelli and D. J. Friedman, "A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology," in IEEE Journal of Solid-State Circuits, vol. 44, no. 4, pp. 1298-1305, April 2009.
[31] R. Bai, S. Palermo and P. Y. Chiang, "2.5 A 0.25pJ/b 0.7V 16Gb/s 3-tap decision-feedback equalizer in 65nm CMOS," 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, 2014, pp. 46-47.
[32] Keysight, “M8048A ISI Channels - Data Sheet”.
[33] J. W. Jung and B. Razavi, “A 25 Gb/s 5.8 mW CMOS equalizer,” IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 515-526, Feb. 2015.
[34] S. Shahramian and A. Chan Carusone, "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS," in IEEE Journal of Solid-State Circuits, vol. 50, no. 7, pp. 1722-1735, July 2015.
[35] K. -Y. Chen, W. -Y. Chen and S. -I. Liu, “A 0.31-pJ/bit 20-Gb/s DFE with 1 discrete tap and 2 IIR filters feedback in 40-nm-LP CMOS,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 64, no. 11, pp. 1282-1286, Nov. 2017.
[36] D. Lee, D. Lee, Y. -H Kim, and L. -S Kim,” A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control,” IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 27, no. 3, pp. 724–728, Mar. 2019.
[37] D. Z. Turker, A. Rylyakov, D. Friedman, S. Gowda, and E. Sanchez-Sinencio, “A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE With Non-Time-Overlapping Data Generation for 4:1 CMOS Clockless Multiplexer,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 67, no. 1, pp. 216–217, Jun. 2020.
[38] S. Shahramian, B. Dehlaghi, and A. C. Carusone, “A 16Gb/s 1 IIR + 1 DT DFE Compensating 28dB Loss with Edge-Based Adaptation Converging in 5μs,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3547-3559, Dec. 2016.
[39] Y.-H Kim, Y. -J Kim, T. -H Lee, and L. -S Kim, “A 21 Gbit/s 1.63-pJ/bit adaptive CTLE and one-tap DFE with single loop spectrum balancing method,” IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 21, no. 2, pp.789–793, Feb. 2016.
[40] Y. -H. Tu, K. -H. Cheng, M. -J. Lee and J. -C. Liu, "A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 7, pp. 2097-2108, July 2018.
[41] Y. Choi, Y. Lee, and C. Kim, “A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 68, no. 10, Oct. 2021.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2023-6-27

推文