使用積分式相位偵測器之低相位雜訊與低參考突波鎖相迴路

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姓名

陳凱琳(Kai-Lin Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

使用積分式相位偵測器之低相位雜訊與低參考突波鎖相迴路
(A Low Phase Noise and Low Reference Spur Phase-Locked Loop Exploiting a Integrated Phase Detector)

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至系統瀏覽論文 (2028-7-31以後開放)

摘要(中)

隨著電路的操作速度日漸提升，設計一個效能良好的時脈產生器必須考量到輸出抖動、雜訊、功率消耗及面積。使用LC震盪器雖然能有較好的雜訊表現，但需要耗費更多的面積，而使用環形震盪器雖然雜訊表現較差，但面積也相對較小。本論文使用環形震盪器，並配合簡單的相位雜訊與參考突波的抑制技巧，達到低面積與低雜訊之目標。
近年來常見用於降低相位雜訊的電路為次取樣鎖相迴路，其藉由迴路鎖定時移除除頻器的方式，有效地降低相位雜訊。然而次取樣相位偵測器在判斷參考時脈與電壓控制震盪器的高頻輸出訊號之相位差時，對於高頻輸出訊號週期性的干擾造成了電路在頻譜上產生嚴重的參考突波。本論文提出另一種相位偵測的方式，將次取樣鎖相迴路的概念，結合時脈與資料回復電路中的積分式相位偵測器，實現不同頻率之間的相位差偵測，並且能在鎖定時移除迴路中的除頻器以降低相位雜訊，同時對電壓控制震盪器的影響最小化，達到低參考突波、低相位雜訊與小面積的效果。
電路設計與佈局採用TSMC 90 nm 1P9M之CMOS製程實現，電路操作電壓為1 V，輸出頻率為2.4 GHz。使用傳統的電荷幫浦鎖相迴路鎖定時，方均根抖動為2.21 ps，輸出相位雜訊在1 MHz的情況下為-104 dBc/Hz，參考突波與主頻率的能量差為-56.5 dBc。使用積分式相位偵測鎖相電路完成鎖定後，方均根抖動降為1.30 ps，輸出相位雜訊在1 MHz的情況下降至-114 dBc/Hz，參考突波與主頻率的能量差為-54.1 dBc。整體電路的功率消耗為3.77 mW，晶片面積為0.80 mm2，其中核心電路面積為0.027 mm2。

摘要(英)

As circuits operate at higher speeds, designing a clock generator with good performance must account for output jitter, noise, power consumption, and area. Although the LC oscillator has better noise performance, it needs to occupy more area, while the ring oscillator has poor noise performance, but the area is relatively small. In this thesis, a small-area and low-noise phase-locked loop (PLL) is implemented using a ring oscillator combined with a simple technique to suppress phase noise and reference spurs.
In recent years, a common circuit used to reduce phase noise is a sub-sampling phase-locked loop(SSPLL), which effectively reduces phase noise by removing the frequency divider when the loop is locked. However, when the sub-sampling phase detector detects a phase difference between the reference clock and the high-frequency output signal of the voltage-controlled oscillator, periodic disturbances cause serious reference spur problems to the high-frequency output signal. Combining the concept of a sub-sampling PLL with a baud-rate phase detector in a clock and data recovery circuit (CDR), an alternative phase detection method is proposed that can detect the phase difference between two different frequencies. After the loop is locked, the divider in the loop is removed, thus reducing the phase noise. At the same time, the interference caused by the phase detector to the VCO is minimized, and low reference spur, low phase noise and small-area PLL circuits are realized.
This work is fabricated in TSMC 90 nm 1P9M CMOS process, the output frequency is 2.4 GHz when the supply voltage is 1V. The measured phase noise of traditional charge pump PLL(CPPLL) at 1 MHz offset -104 dBc/Hz, the rms jitter is 2.21 ps, and reference spur is -56.5 dBc. The measured phase noise of proposed baud-rate phase detect PLL at 1 MHz offset is reduced to -114 dBc/Hz, the rms jitter is reduced to 1.30 ps, and reference spur is -54.1 dBc. The power consumption of the circuit is 3.77 mW. The die area is 0.080 mm2 and active core area is 0.027 mm2.

關鍵字(中)

★ 鎖相迴路
★ 次取樣技術
★ 相位雜訊
★ 參考突波

關鍵字(英)

★ Phase-Locked Loop
★ Sub-sampling Technique
★ Phase Noise
★ Reference Spur

論文目次

摘要 i
Abstract ii
誌謝 iii
目錄 v
圖目錄 vii
表目錄 x
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 2
第2章鎖相迴路先前技術探討 3
2.1 電荷幫浦鎖相迴路系統分析 3
2.2 移除除頻器之鎖相迴路系統分析 7
2.3 迴路雜訊分析 9
2.4 先前架構 11
2.4.1 次取樣鎖相迴路[2] 11
2.4.2 主動式混和相位偵測鎖相迴路[4] 13
2.4.3 輔助相位偵測之鎖相迴路[25] 14
2.4.4 電荷取樣式鎖相迴路[6] 16
2.5 比較與討論 17
第3章使用積分式相位偵測器之鎖相迴路 18
3.1 設計流程 18
3.2 電路架構與操作 19
3.3 使用積分式相位偵測器之鎖相迴路介紹與分析 20
3.3.1 積分式相位偵測器 21
3.3.2 取樣式電荷幫浦[3] 23
3.3.3 脈波產生器[2] 24
3.4 參考突波分析與比較 26
3.4.1 突波介紹[1] 26
3.4.2 取樣式電荷幫浦[3] 29
3.4.3 積分式相位偵測器[11] 30
第4章研究架構設計與實現 32
4.1 鎖頻迴路 33
4.1.1 相位頻率偵測器 33
4.1.2 死區產生器 35
4.1.3 電荷幫浦 37
4.1.4 迴路濾波器 39
4.1.5 電壓控制振盪器 39
4.1.6 除頻器 42
4.2 積分式鎖相迴路 43
4.2.1 積分式相位偵測器 43
4.2.2 取樣式電荷幫浦 45
4.2.3 脈波產生器 46
第5章電路模擬結果 48
5.1 佈局前電路模擬 48
5.1.1 電荷幫浦鎖相迴路模擬 48
5.1.2 積分式鎖相迴路模擬 50
5.2 佈局後模擬 52
5.2.1 電荷幫浦鎖相迴路模擬 52
5.2.2 積分式鎖相迴路模擬 54
5.3 電路佈局 58
5.4 晶片量測環境考量 60
5.5 規格比較 64
第6章結論與未來研究方向 66
6.1 結論 66
6.2 未來研究方向 67
參考文獻 68
附錄-相位雜訊模擬 71

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2023-7-28

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