應用於高速鏈結之數位化介面電路技術

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呂鴻文(Hung-wen Lu) 查詢紙本館藏

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論文名稱

應用於高速鏈結之數位化介面電路技術
(Digitalized I/O techniques for high speed serial link system)

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摘要(中)

當許多序列式輸入輸出介面整合在一顆晶片上時﹐這個系統對外的導線數目與介面電路的元件可以大幅的減少﹐也可藉此達到更低的功率消耗與更高的頻寬.雖然之前序列電路相關的研究已經可以達到每秒數億筆資料的傳輸速度﹐但就每一個單一通道本身而言都耗費大量的面積與高功率﹐這使得將多組的序列介面系統整合入一顆晶片變得困難.
為了減少系統的功率消耗與電路成本﹐同時提升設計在不同製程間的移轉性﹐本論文以數位化的精神分別改善五個在序列傳輸介面的重要模組.第一個模組是使用低頻率多相位參考時脈的樹狀多工器﹐不需要高頻率單相位參考時脈﹐提出的多工器以多級實現﹐電路內部節點的寄生電容值較小﹐因此可達到較高的頻寬﹐同時也對製程飄移較不敏感﹐第二個模組是僅用反相器單元與傳輸閘單元組成的預先驅動電路與預先放大電路﹐此電路可隨著供應電壓而動態調整性能同時也大幅降低功率消耗與電路面積﹐另外我們提出了具電感效應的自我偏壓電路﹐可以降低切換雜訊同時提升操作頻寬.第三個模組是低靜態功率消耗的低壓差動式輸出驅動電路.透過同步切換雜訊減少電路與輸出準位自我校正電路﹐此電路可以減少50%的靜態功率消耗同時減少製程飄移所帶來的影響.第四個模組是資料相位校正式的時脈與資料回復電路﹐它使用由數位緩衝電路構成的數位控制延遲電路來達到高頻寬、高輸入敏感度與低硬體消耗﹐另外採用低頻率多相位的參考時脈來降低數位迴路中相位處理電路的頻寬﹐此數位迴路透過可程式化計數器來改變頻寬﹐進而在鎖定速度與過濾雜訊的效能中取得平衡﹐最後一個模組是全數位的電感電容式震盪電路﹐藉由電感電容共震的帶通特性達到較低的相位雜訊﹐完成針對此電路的小訊號模型、震盪頻率與電路參數的計算﹐在此也提出一數位控制電感元件來補償製程飄移造成的電感值飄移﹐同時也提出一高解析度的數位控制電容元件來達到較高的頻率解析度。

摘要(英)

With many high-speed serial I/Os integrated on a chip, the component count and power budget of a system can be significantly reduced, allowing for both reduced costs and expanded capability. Although previously published designs have achieved multi-gigabit bandwidth per channel, the area and power consumption are too large to make terabit integrated circuits feasible.
This thesis is focus on the design low power and area efficient serial I/O system. Five main building blocks are discussed in this thesis. The first topic proposes a tree-topology multiplexer that uses a multi-phase low-frequency clock instead of a high frequency clock. The parasitic effects at each stage are minimized by multiplexing only two inputs. Therefore, the jitter caused by the process variation and ISI are reduced, and the data rate is increased. In the second topic, a pre-driver and a pre-amplifier composed of inverters and transmission gates only are proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. The third topic is an all-digital LVDS output driver design. A simultaneous switching noise reduction technique and an auto calibration mechanism are implemented to suppress switching noise and to handle process and environmental variations. The fourth topic is an all-digital deskew buffer. Its delay line circuits adopt digital inductive biasing loads to achieve high bandwidth and with a high input sensitivity. With a multi-phase reference clocks, the bandwidth requirements of the following digital signal processing circuits is thus released. A programmable confidence counter is adopted to adjust the loop bandwidth and filter high-frequency data jitter. The last topic is a digital DCO architecture with novel scheme for inductor and varactor. By using the band-pass characteristic of LC tank oscillation, it is effective for phase noise reduction in the proposed DCO. Related small signal model analysis helps calculate oscillation frequency and adjust the circuit parameters. We use the programmable inductor and varactors to solve the process variation problem and obtain the central frequency and tuning range. By using logic cell only, the proposed architecture has a high portability and low hardware overhead.

關鍵字(中)

★ 數位控制震盪電路
★ 全數位鎖相迴路
★ 時脈與資料回復電路
★ 序列器
★ 多工器
★ 介面電路
★ 收發電路
★ 發射電路
★ 接收電路

關鍵字(英)

★ Digital control oscillator
★ All digital phase lock loop
★ Clock and data recovery
★ Seriallizer
★ Multiplexer
★ I/O
★ Transceiver
★ Interface

論文目次

CHAPTER 1 INTRODUCTION 1
1.1 LINK COMPONENTS 1
1.2 THESIS ORGANIZATION 3
CHAPTER 2 TREE-TOPOLOGY MULTIPLEXER 6
2.1 MUX ARCHITECTURE OVERVIEW 6
2.2 PROPOSED MUX ARCHITECTURE 8
2.3 MUX TIMING JITTER ANALYSIS 11
2.3.1 Jitter caused by process variation 12
2.4 MUX ISI JITTER ANALYSIS 15
2.4.1 ISI jitter calculation for single-stage MUX 15
2.4.2 ISI jitter calculation for the proposed MUX 16
2.4.3 Power comparison among different MUX architectures 20
2.5 MUX TEST CHIP IMPLEMENTATION AND MEASUREMENT 23
CHAPTER 3 PRE-DRIVER AND PRE-AMPLIFIER 27
3.1 BUFFER MOTIVATION 27
3.2 BUFFER ARCHITECTURE 28
3.2.1 Original digital buffer 28
3.2.2 Proposed digital buffer 29
3.3 FREQUENCY PEAKING ANALYSIS 31
3.4 BUFFER COMPARISON SIMULATION 34
3.5 BUFFER TEST CHIP IMPLEMENTATION AND MEASUREMENT 37
CHAPTER 4 LVDS OUTPUT DRIVER 42
4.1 LVDS DRIVER MOTIVATION 42
4.2 DIGITAL LVDS DRIVER 43
4.2.1 Driver architecture 43
4.2.2 PVT variation consideration 45
4.3 SSN-REDUCED PRE-DRIVER 47
4.3.1 Distributed-and-Weighted Pre-driver 47
4.3.2 Duty Cycle Adjustment 51
4.3.3 Process variation and driver comparison 57
4.4 LVDS TEST CHIP IMPLEMENTATION AND MEASUREMENT 60
4.4.1 Eye diagram measurement 62
4.4.2 Calibration function testing 65
CHAPTER 5 DESKEW BUFFER 69
5.1 DESKEW BUFFER MOTIVATION 69
5.2 REPORTED CDR DESIGNS OVERVIEW 70
5.3 DESKEW BUFFER SYSTEM ARCHITECTURE AND ANALYSIS 76
5.3.1 Acquisition time 77
5.3.2 Loop latency 77
5.3.3 Frequency tolerance 79
5.3.4 Loop bandwidth 81
5.4 DSKEW BUFFER CIRCUIT DESIGN 82
5.4.1 DCDL 82
5.4.2 PD, CC, and FSM circuit design 86
5.5 DESKEW BUFFER TEST CHIP IMPLEMENTATION 90
5.5.1 Chip architecture and test circuits design 90
5.5.2 Measurement and comparisons 92
CHAPTER 6 DIGITAL CONTROL OSCILLATOR 98
6.1 DCO MOTIVATION 98
6.2 PROPOSED DCO ARCHITECTURE 101
6.3 DIGITAL CONTROL INDUCTOR 102
6.4 DIGITAL CONTROL VARACTOR 105
6.5 OSCILLATION BEHAVIOR ANALYSIS 108
6.5.1 Transfer function calculation 108
6.5.2 Calculation and simulation results 111
6.6 DCO TEST CHIP IMPLEMENTATION 114
CHAPTER 7 CONCLUSION AND FUTURE WORK 119
7.1 CONCLUSION 119
7.2 FUTURE WORK 121
REFERENCE 123

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指導教授

劉建男、蘇朝琴
(Chien-Nan Jimmy Liu、Chau-chin Su)

審核日期

2008-11-11

推文