應用於第五代行動通訊毫米波頻段之 CMOS 單刀雙擲開關與中功率放大器

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姓名

蔡祈安(Chi-An Tsai) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於第五代行動通訊毫米波頻段之 CMOS 單刀雙擲開關與中功率放大器
(CMOS SPDT Switches and Medium Power Amplier for 5G Millimeter-Wave Bands)

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至系統瀏覽論文 (2026-8-10以後開放)

摘要(中)

在本論文中，我們使用 90-nm CMOS 製程設計之非對稱式收發
開關以及中功率放大器，以及使用 0.18-µm CMOS 製程來實現 Ka 頻
段之行進波開關。
在第二章，我們設計一個應用於 Ka 頻段之行進波開關，操作
頻率設計在 26.5 GHz 至 40 GHz。本電路利用行進波的概念實現寬
頻開關，藉由電感性的傳輸線與 o-state 的電晶體來形成一仿真
（artical）傳輸線。量測結果在 26.5 至 40 GHz 的操作頻率範圍，植
入損耗小於 3.17 dB，返回損耗大於 9.1 dB，隔離度大於 28.4 dB。在
35 GHz 下的大訊號量測結果 IP1dB 為 17.5 dBm。
在第三章，我們設計一個應用於 Q 頻段的非對稱式收發開關，操
作頻率範圍為 37 GHz 至 44 GHz。架構主要是由 Π-network 的濾波
器架構來實現。在操作頻率範圍 3744 GHz 內的量測結果，TX mode
的植入損耗小於 1.56 dB，而 RX mode 植入損耗小於 1.5 dB，返回損
耗在 TX mode 皆有大於 11.1 dB，RX mode 皆大於 11.9 dB。隔離度
在 TX mode 跟 RX mode 皆分別大於 24.6 dB 與 16.3 dB。在 40 GHz
下模擬大訊號得到的 IP1dB 為 40.4 dBm。
在第四章提出一個應用於 5G 毫米波之使用中和電容技術之中功
率放大器，操作頻率設計在 37 GHz 至 43.5 GHz。本電路輸入輸出由
變壓器來作單端與差動的轉換，利用挑選中和電容與電路 CG 級的
閘級電容來達到最佳的穩定效果與最大可用增益。量測結果增益大於
10.6 dB、輸入返回損耗大於 8.7 dB、輸出返回損耗大於 2.8 dB，輸
出返回損耗有比較明顯往低頻偏移的趨勢。在 40 GHz 時， OP1dB 及
在 OP1dB 下的 PAE 分別為 12.4 dBm 及 7.9%。

摘要(英)

In this paper, we use the 90-nm CMOS process to design an asymmetric T/R switch and a medium power amplier, we also use the 0.18-m
CMOS process to implement a traveling wave switch for the Ka band.
In the second chapter of this paper, we design a traveling wave
switch for the Ka band with an operating frequency range of 26.5 GHz
to 40 GHz.This circuit utilizes the concept of a traveling wave to achieve
wideband switch.By combining inductive transmission lines and o-state
transistor, an articial transmission line is formed.The measurement
results show that within the operating frequency range of 26.5 to 40
GHz, the insertion loss is less than 3.17 dB, the return loss is greater
than 9.1 dB, and the isolation is greater than 28.4 dB.
In Chapter 3, we design a asymmetric T/R switch operation in the
37 GHz to 44 GHz frequency range. The architecture is primarily based
on a Π-network-lter structure.In the operating frequency range of 37-
44 GHz, the insertion loss of the TX mode is less than 1.56 dB, The
return loss is greater than 11.1 dB in TX mode and greater than 11.9
dB in RX mode.The isolation is greater than 24.6 dB and 16.3 dB in
TX and RX modes, respectively.At 40 GHz, the simulated large-signal
IP1dB is measured to be 40.4 dBm.
In Chapter 4, we propose a medium power amplier using capacitance neutralization technique for the 5G millimeter-wave. The operating frequency range is designed from 37 GHz to 43.5 GHz. The
circuit utilizes transformers to achieve single-ended to dierential conII
version.By selecting neutralization capacitors and circuit CG-stage gate
capacitor, the circuit achieves optimal stable stability and maximum
available gain.The measurement results show a gain greater than 10.6
dB, input return loss greater than 8.7 dB, output return loss greater
than 2.8 dB. The output return loss exhibits a noticeable trend towards
lower frequencies. At 40 GHz, the PAE of OP1dB and OP1dB are 12.4
dBm and 7.9%.

關鍵字(中)

★ 功率放大器
★ 毫米波
★ 收發開關
★ 行進波開關

關鍵字(英)

★ Power Amplifier
★ Millimeter Wave
★ T/R Switch
★ Traveling Wave Switch

論文目次

頁次
摘要. . . . II
Abstract . . . . III
目錄 . . . . V
圖目錄 . . . . VII
表目錄 . . . . XI
第一章緒論 . . . . 1
1.1 研究動機與背景 . . . . 1
1.2 毫米波開關文獻回顧 . . . . 3
1.3 論文架構 . . . . 4
第二章 Ka 頻段行波單刀雙擲開關. . . . 5
2.1 簡介 . . . . 5
2.2 電晶體模型 . . . . 6
2.3 基體浮接技術 . . . . 7
2.4 電路模擬與量測. . . . 8
2.4.1 電路設計. . . . . 8
2.4.2 模擬結果 . . . 15
2.4.3 量測結果 . . . . 20
2.5 結果與討論 . . . . 24
第三章 Q 頻段非對稱式收發開關 . . . . 27
3.1 簡介. . . . 27
3.2 收發開關介紹 . . . . 28
3.2.1 收發開關類型 . . . . 28
3.2.2 對稱式開關與非對稱式開關. . . . 29
3.3 電路模擬與量測. . . . 30
3.3.1 電路設計. . . . . 30
3.3.2 模擬結果. . . . 33
3.3.3 量測結果. . . . . 39
3.3.4 電路偵錯與重新模擬 . . . . 45
3.4 結果與討論 . . . . 50
第四章應用於 5G 毫米波 n259/n260 頻段之中功率放大器 . 53
4.1 簡介 . . . . 53
V
4.2 電路模擬與量測 . . . 54
4.2.1 電路設計 . . . . 54
4.2.2 模擬結果 . . . 67
4.2.3 量測結果 . . . . 72
4.2.4 電路偵錯與重新模擬. . . . 76
4.3 結果與討論. . . . 78
第五章結論 . . . . 79
參考文獻. . . . 81

參考文獻

[1] M. Ahn, B. S. Kim, C.-H. Lee, and J. Laskar, A high power
CMOS switch using substrate body switching in multistack structure, IEEE Microw. Wireless Compon. Lett., vol. 17, no. 9, pp.
682684, Sep. 2007.
[2] K.-Y. Lin, W.-H. Tu, P.-Y. Chen, H.-Y. Chang, H. Wang, and
R.-B. Wu, Millimeter-wave MMIC passive HEMT switches using traveling-wave concept, IEEE Trans. Microw. Theory Techn.,
vol. 52, no. 8, pp. 17981808, Aug. 2004.
[3] X. J. Li and Y. P. Zhang, Flipping the CMOS switch, IEEE Microw. Mag., vol. 11, no. 1, pp. 8696, Feb. 2010.
[4] R. Dilli, Analysis of 5G wireless systems in FR1 and FR2 frequency
bands, 2nd Int. Conf. Innov. Mech. Ind. Appl. (ICIMIA), pp. 767
772, Mar. 2020.
[5] A. Mamane, M. Fattah, M. El Ghazi, and M. El Bekkali, 5G enhanced mobile broadband (eMBB): Evaluation of scheduling algorithms performances for Time-Division Duplex mode, Int. J. Interact. Mob. Technol, vol. 16, p. 121, Mar. 2022.
[6] F.-J. Huang and K. O, A 0.5 µm CMOS T/R switch for 900-MHz
wireless applications, IEEE J. Solid-State Circuits, vol. 36, no. 3,
pp. 486492, Mar. 2001.
81
[7] B.-W. Min and G. M. Rebeiz, Ka-band low-loss and high-isolation
0.13 µm CMOS SPST/SPDT switches using high substrate resistance, IEEE Radio Freq. Integr. Circuits Symp, pp. 569572, Jun.
2007.
[8] C.-Y. Ou, C.-Y. Hsu, H.-R. Lin, and H.-R. Chuang, A highisolation high-linearity 24-GHz CMOS T/R switch in the 0.18-µm
CMOS process, Eur. Microw. Integr. Circuits Conf, pp. 250253,
Sep. 2009.
[9] S.-C. Chang, S.-F. Chang, T.-Y. Chih, and J.-A. Tao, An
internally-matched high-isolation CMOS SPDT switch using leakage cancellation technique, IEEE Microw. Wireless Compon. Lett.,
vol. 17, no. 7, pp. 525527, Jul. 2007.
[10] Y.-P. Zhang, Q. Li, W. Fan, C. H. Ang, and H. Li, A dierential
CMOS T/R switch for multistandard applications, IEEE Trans.
Circuits Syst. II, vol. 53, no. 8, pp. 782786, Aug. 2006.
[11] A. Dyskin, N. Peleg, S. Wagner, D. Ritter, and I. Kallfass, An
asymmetrical 6090 GHz single-pole double throw switch MMIC,
Proc. Eur. Microw. Integr. Circuits Conf, pp. 145148, Oct. 2013.
[12] K.-H. Lee, S. Choi, and C.-Y. Kim, A 2530 GHz asymmetric
SPDT switch for 5G applications in 65-nm triple-well CMOS, IEEE
Microw. Wireless Compon. Lett., vol. 29, no. 6, pp. 391393, Jun.
2019.
82
[13] W. Lee and S. Hong, Low-loss and small-size 28 GHz CMOS SPDT
switches using switched inductor, IEEE Radio Freq. Integr. Circuits Symp, pp. 148151, Jun. 2018.
[14] B. Razavi, Design of Analog CMOS Integrated Circuits. McGrawHill, 2001.
[15] M.-C. Yeh, Z.-M. Tsai, R.-C. Liu, K.-Y. Lin, Y.-T. Chang, and
H. Wang, Design and analysis for a miniature CMOS SPDT
switch using body-oating technique to improve power performance, IEEE Trans. Microw. Theory Techn., vol. 54, no. 1, pp.
3139, Jan. 2006.
[16] M. J. Schindler and A. Morris, DC-40 GHz and 20-40 GHz MMIC
SPDT switches, IEEE Trans. Microw. Theory Techn., vol. 35,
no. 12, pp. 14861493, 1987.
[17] J. Kim, W. Ko, S.-H. Kim, J. Jeong, and Y. Kwon, A highperformance 40-85 GHz MMIC SPDT switch using FET-integrated
transmission line structure, IEEE Microw. Wireless Compon.
Lett., vol. 13, no. 12, pp. 505507, Dec. 2003.
[18] K.-T. Ho, A 3.5-GHz GaN and Ka-bnad GaAs power ampliers
using wilkinson power combiner, Master′s thesis, National Central
University, 2022.
[19] K. T. Trinh, H.-L. Kao, H.-C. Chiu, and N. C. Karmakar, A Kaband GaAs MMIC traveling-wave switch with absorptive charac83
teristic, IEEE Microw. Wireless Compon. Lett., vol. 29, no. 6, pp.
394396, Jun. 2019.
[20] Z.-M. Tsai, M.-C. Yeh, M.-F. Lei, H.-Y. Chang, C.-S. Lin, and
H. Wang, DC-to-135 GHz and 15-to-135 GHz SPDT traveling wave
switches using FET-integrated CPW line structure, IEEE MTT-S
Int. Microw. Symp, pp. 13931396, Jun. 2005.
[21] H.-Y. Chang and C.-Y. Chan, A low loss high isolation DC-60 GHz
SPDT traveling-wave switch with a body bias technique in 90 nm
CMOS process, IEEE Microw. Wireless Compon. Lett., vol. 20,
no. 2, pp. 8284, Feb. 2010.
[22] M.-C. Yeh, Z.-M. Tsai, and H. Wang, A miniature DC-to-50 GHz
CMOS SPDT distributed switch, Eur. Microw. Conf, vol. 3, p. 4,
Oct. 2005.
[23] B.-W. Min and G. M. Rebeiz, A compact DC-30 GHz 0.13-µm
CMOS SP4T switch, IEEE Topical Meeting on Silicon Monolithic
Integrated Circuits in RF Systems (SiRF), pp. 14, Jan. 2009.
[24] B. W. Min and G. M. Rebeiz, Ka-band low-loss and high-isolation
switch design in 0.13-µm CMOS, IEEE Trans. Microw. Theory
Techn., vol. 56, no. 6, pp. 13641371, Jun. 2008.
[25] C. Liu, Q. Li, and Y.-Z. Xiong, A compact Ka-band SPDT switch
with high isolation, IEEE Int. Symp. Integr. Circuits. (ISIC), pp.
304307, Dec. 2014.
84
[26] T. Despoisse, N. Deltimple, A. Ghiotto, M. De Matos, J. Forest, and
P. Busson, An integrated 65-nm CMOS SOI Ka-band asymmetrical
single-pole double-throw switch based on hybrid couplers, IEEE
Microw. Wireless Compon. Lett., vol. 30, no. 12, pp. 11571160,
Dec. 2020.
[27] J. Park, W. Lee, and S. Hong, A small-size K-band SPDT switch
using alternate CMOS structure with resonating inductor matching, IEEE Microw. Wireless Compon. Lett., vol. 30, no. 11, pp.
10931096, Nov. 2020.
[28] J.-S. Fu, A novel X-band CMOS asymmetric T/R switch with highpass TX arm and low-pass RX arm, accepted by Electron. Lett.,
2023.
[29] M. Uzunkol and G. Rebeiz, A low-loss 5070 GHz SPDT switch in
90 nm CMOS, IEEE J. Solid-State Circuits, vol. 45, no. 10, pp.
20032007, Sep. 2010.
[30] S.-F. Chao, H. Wang, C.-Y. Su, and J. G. Chern, A 50 to 94-GHz
CMOS SPDT switch using traveling-wave concept, IEEE Microw.
Wireless Compon. Lett., vol. 17, no. 2, pp. 130132, Feb. 2007.
[31] X. Meng and C. P. Yue, Compact millimeter-wave SPDT switches
and wilkinson power combiners implemented by LC-based spiral
transmission lines, IEEE Trans. Microw. Theory Techn., vol. 69,
no. 2, pp. 13051315, Feb. 2020.
85
[32] X. Fu, Y. Wang, Z. Li, A. Shirane, and K. Okada, A 68-dB isolation
1.0-dB loss compact CMOS SPDT RF switch utilizing switched
resonance network, IEEE MTT-S Int. Microw. Symp, pp. 1315
1318, Aug. 2020.
[33] J. Zhang, T. Wu, L. Nie, S. Ma, Y. Chen, and J. Ren, A 120150
GHz power amplier in 28-nm CMOS achieving 21.9-dB gain and
11.8-dBm Psat for sub-THz imaging system, IEEE Access, vol. 9,
pp. 74 75274 762, May 2021.
[34] A. F. Tong, W. M. Lim, C. B. Sia, K. S. Yeo, Z. L. Teng, and P. F.
Ng, RF CMOS unit width optimization technique, IEEE Trans.
Microw. Theory Techn., vol. 55, no. 9, pp. 18441853, 2007.
[35] W. L. Chan, J. R. Long, M. Spirito, and J. J. Pekarik, A 60 GHzband 1V 11.5 dBm power amplier with 11% PAE in 65nm CMOS,
IEEE Int. Solid-State Circuits Conf. Tech. Dig., pp. 380381,381a,
2009.
[36] W.-C. Sun and C.-N. Kuo, A 19.1% PAE, 22.4-dBm 53-GHz parallel power combining power amplier with stacked-FET techniques
in 90-nm CMOS, IEEE MTT-S Int. Microw. Symp, pp. 327330,
Jun. 2019.
[37] H. Asada, K. Matsushita, K. Bunsen, K. Okada, and A. Matsuzawa,
A 60 GHz CMOS power amplier using capacitive cross-coupling
neutralization with 16 % PAE, Eur. Microw. Conf, pp. 11151118,
Oct. 2011.
86
[38] M. L. Edwards and J. H. Sinsky, A new criterion for linear 2-
port stability using a single geometrically derived parameter, IEEE
Trans. Microw. Theory Techn., vol. 40, no. 12, pp. 23032311, Dec.
1992.
[39] Abidi, General relations between IP2, IP3, and osets in dierential
circuits and the eects of feedback, IEEE Trans. Microw. Theory
Techn., vol. 51, no. 5, pp. 16101612, May 2003.
[40] T. LaRocca and M.-C. F. Chang, 60 GHz CMOS dierential and
transformer-coupled power amplier for compact design, IEEE Radio Freq. Integr. Circuits Symp, pp. 6568, Jun. 2008.
[41] D. Chowdhury, P. Reynaert, and A. M. Niknejad, Design considerations for 60 GHz transformer-coupled CMOS power ampliers,
IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 27332744, Oct.
2009.
[42] H. Shigematsu, T. Hirose, F. Brewer, and M. Rodwell, Millimeterwave CMOS circuit design, IEEE Trans. Microw. Theory Techn.,
vol. 53, no. 2, pp. 472477, Feb. 2005.
[43] J. Jia, X. Wang, and J. Wen, A 40-GHz power amplier with output power of 15.2 dBm in 65-nm CMOS, IEEE MTT-S Int. Wireless Symp, pp. 13, May 2021.
[44] M. A. Masud, H. Zirath, M. Ferndahl, and H.-O. Vickes, 90 nm
CMOS MMIC amplier, pp. 201204, Jun. 2004.
87
[45] Y. Jin, M. A. Sanduleanu, E. A. Rivero, and J. R. Long, A
millimeter-wave power amplier with 25dB power gain and+ 8dBm
saturated output power, Eur. Solid State Circuits Conf. (ESSCIRC), pp. 276279, Sep. 2007.
[46] S. N. Ali, P. Agarwal, L. Renaud, R. Molavi, S. Mirabbasi, P. P.
Pande, and D. Heo, A 40% PAE frequency-recongurable CMOS
power amplier with tunable gatedrain neutralization for 28-GHz
5G radios, IEEE Trans. Microw. Theory Techn., vol. 66, no. 5, pp.
22312245, May 2018.
[47] S. Shakib, H.-C. Park, J. Dunworth, V. Aparin, and K. Entesari,
A highly ecient and linear power amplier for 28-GHz 5G phased
array radios in 28-nm CMOS, IEEE J. Solid-State Circuits, vol. 51,
no. 12, pp. 30203036, Dec. 2016.
[48] Y.-C. Lee, T.-Y. Chen, and J. Y.-C. Liu, An adaptively biased
stacked power amplier without output matching network in 90-
nm CMOS, IEEE MTT-S Int. Microw. Symp, pp. 16671690, Jun.
2017.
[49] H.-T. Dabag, B. Hana, F. Golcuk, A. Agah, J. F. Buckwalter, and
P. M. Asbeck, Analysis and design of stacked-FET millimeter-wave
power ampliers, IEEE Trans. Microw. Theory Techn., vol. 61,
no. 4, pp. 15431556, Apr. 2013.
[50] P. Yan, J. Chen, W. Hong, and X. Jiang, A 42 to 56 GHz wide band
CMOS power amplier, Millim. Waves THz Technol. Workshop
88
(UCMMT), pp. 12, Sep. 2013.
[51] M. Bassi, J. Zhao, A. Bevilacqua, A. Ghilioni, A. Mazzanti, and
F. Svelto, A 4067 GHz power amplier with 13 dbm psat and 16%
pae in 28 nm CMOS LP, IEEE J. Solid-State Circuits, vol. 50,
no. 7, pp. 16181628, Mar. 2015.
[52] C.-W. Wu, Y.-H. Lin, Y.-H. Hsiao, C.-F. Chou, Y.-C. Wu, and
H. Wang, Design of a 60-GHz high-output power stacked-FET
power amplier using transformer-based voltage-type power combining in 65-nm CMOS, IEEE Trans. Microw. Theory Techn.,
vol. 66, no. 10, pp. 45954607, Oct. 2018.

指導教授

傅家相(Jia-Shiang Fu)

審核日期

2023-8-14

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