博碩士論文 110522047 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:173 、訪客IP:18.119.102.149
姓名 吳定濂(Ding-Lian Wu)  查詢紙本館藏   畢業系所 資訊工程學系
論文名稱 衛星上可重組化計算之安全FPGA動態部分可重組架構
(Secure FPGA Dynamic Partial Reconfiguration Architecture for Reconfigurable Computing on Satellites)
相關論文
★ 基於OP-TEE的可信應用程式軟體生態系統★ SeFence: 基於安全感測的可信任周邊存取控制
★ 高解析度二維地理影像的三維建模:旋轉變換投影與傳統方法的比較研究★ 在低軌道衛星無線通訊中的CSI預測方法
★ 為多流量低軌道衛星系統提出的動態換手策略★ 基於Trustzone的智慧型設備語音隱私保護系統
★ 一種減輕LEO衛星網路干擾的方案★ TruzGPS:基於TrustZone的位置隱私權保護系統
★ 衛星地面整合網路之隨機接入前導訊號設計與偵測★ SatPolicy: 基於Trustzone的衛星政策執行系統
★ TruzMalloc: 基於TrustZone 的隱私資料保 護系統★ 衛星地面網路中基於物理層安全的CSI保護方法
★ 低軌道衛星地面整合網路之安全非正交多重存取傳輸★ 低軌道衛星地面網路中的DRX機制設計
★ 衛星地面整合網路之基於集合系統的前導訊號設計★ 基於省電的低軌衛星網路路由演算法
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 ( 永不開放)
摘要(中) 衛星與可重組化計算相結合,為系統提供更高的靈活性和適應性。然而,缺乏安全的更新途徑可能導致惡意硬體木馬的植入或攻擊者竊取機密硬體設計。現有的安全更新機制無法有效阻擋惡意重組或讀回攻擊,使得可重組介面面臨重大威脅。因此,我們的設計利用可信執行環境(TEE)來構建安全的 FPGA 動態部分可重組方案,有效保護 FPGA 免受攻擊者侵害。最後,我們在 Xilinx Zynq UltraScale+ MPSoC 設備上實現了該方案,並評估了其時間和空間開銷。
摘要(英) Satellites combined with reconfigurable computing offer higher flexibility and adaptability to systems. However, the lack of a secure update path can lead to the implantation of malicious hardware Trojans or the theft of confidential hardware designs by attackers. Existing security update mechanisms are unable to effectively block malicious reconfiguration or readback attacks, exposing the reconfiguration interface to significant threats. Therefore, our design utilizes a trusted execution environment (TEE) to construct a secure FPGA dynamic partial reconfiguration scheme that effectively protects the FPGA from attackers. Finally, we implemented the scheme on the Xilinx Zynq UltraScale+ MPSoC device to evaluate its time and space overhead.
關鍵字(中) ★ FPGA 更新
★ 動態部分可重組
★ 可重組化計算
★ 可信執行環境
★ ARM TrustZone
關鍵字(英) ★ FPGA Update
★ Dynamic Partial Reconfiguration
★ Reconfigurable Computing
★ Trusted Execution Environment
★ ARM TrustZone
論文目次 中文摘要 i
Abstract ii
致謝 iii
Contents iv
List of Figures vi
List of Tables vii
1 Introduction 1
2 Background 5
2.1 ARM TrustZone 5
2.2 Xilinx FPGA Reconfiguration Interface 6
2.3 Dynamic Partial Reconfiguration 7
2.4 Threat Model 8
3 Related Works 9
4 Design and Implementation 14
4.1 Trust Reconfiguration Interface 14
4.2 Normal World 16
4.2.1 Remove normal world PL update component 16
4.2.2 Bitstream Downloader 16
4.2.3 Initiate PL update 16
4.3 Secure World 17
4.3.1 Response to PL update request from REE 18
4.3.2 Interface to access CSU (PL manager PTA) 18
4.3.3 DMA driver 18
4.3.4 AES driver 19
4.3.5 PCAP driver 22
4.4 Encrypted bitstream 24
4.4.1 Unencrypted header 24
4.4.2 Encrypted image 25
4.5 Isolate driver 25
4.6 TrustFURE Data and Control Flow 26
5 Evaluation 30
5.1 Security Analysis 30
5.2 Experimental Setup 31
5.3 Performance Evaluation 32
5.3.1 Minimizing Trusted Computing Base (TCB) 32
5.3.2 Execution Time of Reconfiguration 33
6 Future Work and Conclusion 35
Bibliography 36
參考文獻 [1] G. Yang, J. Lei, W. Xie, Z. Fang, Y. Li, J. Wang, and X. Zhang, “Algorithm/hardware codesign for real-time on-satellite cnn-based ship detection in sar imagery,” IEEE Transactions on Geoscience and Remote Sensing, vol. 60, pp. 1–18, 2022.
[2] Xilinx, “Radiation tolerant kintex ultrascale product,” 2023, [Online; accessed 30-May-2023]. [Online]. Available: https://www.xilinx.com/products/silicon-devices/fpga/rt-kintex-ultrascale.html
[3] Microchip, “Radiation-tolerant field programmable gate arrays (fpgas),” 2023, [Online; accessed 30-May-2023]. [Online]. Available: https://www.microchip.com/en-us/products/fpgas-and-plds/radiation-tolerant-fpgas
[4] NASA, “Integrated circuits (microcircuits) manufacturing, general specification for,” 2002, [Online; accessed 30-May-2023]. [Online]. Available: https://nepp.nasa.gov/DocUploads/591D8C5B-C750-4462-B37E007D578B121D/MIL-PRF-38535.pdf
[5] AMD, “Amd announces completion of class b qualification for first space-grade versal adaptive socs enabling on-board ai processing in space,” 2022, [Online; accessed 30-May-2023]. [Online]. Available: https://www.amd.com/en/newsroom/press-releases/2022-11-15-amd-announces-completion-of-class-b-qualification-.html
[6] W. Lie and W. Feng-yan, “Dynamic partial reconfiguration in fpgas,” in 2009 Third International Symposium on Intelligent Information Technology Application, vol. 2, 2009, pp. 445–448.
[7] M. Tehranipoor and F. Koushanfar, “A survey of hardware trojan taxonomy and detection,” IEEE Design & Test of Computers, vol. 27, no. 1, pp. 10–25, 2010.
[8] T. Zhang, M. Tehranipoor, and F. Farahmandi, “Bitfree: On significant speedup and security applications of fpga bitstream format reverse engineering,” in 2023 IEEE European Test Symposium (ETS), 2023, pp. 1–6.
[9] M. Cho, D. Lee, S. Lee, Y. Kim, and H.-M. Lee, “Automated reverse engineering tools for fpga bitstream extraction and logic estimation,” in 2022 19th International SoC Design Conference (ISOCC), 2022, pp. 328–329.
[10] F. Unterstein, N. J. amd Neil Hanley, C. Gu, and J. Heyszl, “Sca secure and updatable crypto engines for fpga soc bitstream decryption: extended version,” in 2021 Journal of Cryptographic Engineering, 2021, pp. 1–16.
[11] F. Unterstein, T. Sel, T. Zeschg, N. Jacob, M. Tempelmeier, M. Pehl, and F. D. Santis, “Secure update of fpga-based secure elements using partial reconfiguration,” Cryptology ePrint Archive, Paper 2020/833, 2020, https://eprint.iacr.org/2020/833. [Online]. Available: https://eprint.iacr.org/2020/833
[12] J. Vliegen, M. M. Rabbani, M. Conti, and N. Mentens, “Sacha: Self-attestation of configurable hardware,” in 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2019, pp. 746–751.
[13] N. Khan, S. Nitzsche, A. G. López, and J. Becker, “Utilizing and extending trusted execution environment in heterogeneous socs for a pay-per-device ip licensing scheme,” IEEE Transactions on Information Forensics and Security, vol. 16, pp. 2548-2563, 2021.
[14] R. Kuramoto, “Xapp1267(v1.6) using encryption and authentication to secure an ultrascale/ ultrascale+ fpga bitstream,” 2023. [Online]. Available: https://docs.xilinx.com/r/en-US/xapp1267-encryp-efuse-program/Using-Encryption-and-Authentication-to-Secure-an-UltraScale/UltraScale-FPGA Bitstream-Application-Note
[15] ARM.org, “Arm trustzone technology,” 2023, [Online; accessed 30-May-2023]. [Online]. Available: https://developer.arm.com/Processors/TrustZone%20for%20Cortex-A
[16] Trusted Execution Environment, [Online; accessed 30-May-2023]. [Online]. Available: https://en.wikipedia.org/wiki/Trusted_execution_environment
[17] ARM Limited, “Smc calling convention 1.4 bet1,” 2023, [Online; accessed 30-May-2023]. [Online]. Available: https://documentation-service.arm.com/static/622799018804d00769e9b345
[18] ——, “Arm architecture reference manual security extensions supplement,” 2023, [Online; accessed 30-May-2023]. [Online]. Available: https://developer.arm.com/documentation/ddi0309/f/Memory-and-System-Architecture/Register-1--control-registers/Secure-Configuration-Register?lang=en
[19] ——, “Arm address channel signals,” 2023, [Online; accessed 30-May-2023]. [Online]. Available: https://developer.arm.com/documentation/ddi0301/h/level-two-interface/axi-control-signals-in-the-processor/address-channel-signals
[20] Xilinx, “Ug1085 zynq ultrascale+ device technical reference manual,” 2020, [Online; accessed 30-May-2023]. [Online]. Available: https://docs.xilinx.com/v/u/en-US/ug1228-ultrafast-embedded-design-methodology-guide
[21] Trusted computing base, [Online; accessed 30-May-2023]. [Online]. Available: https://en.wikipedia.org/wiki/Trusted_computing_base
[22] S. S. Math, R. B. Manjula, S. S. Manvi, and P. Kaunds, “Data transactions on system-on-chip bus using axi4 protocol,” in 2011 INTERNATIONAL CONFERENCE ON RECENT ADVANCEMENTS IN ELECTRICAL, ELECTRONICS AND CONTROL ENGINEERING, 2011, pp. 423–427.
[23] Dynamic Function eXchange Controller v1.0 LogiCORE IP Product Guide, 2020, [Online; accessed 30-May-2023]. [Online]. Available: https://docs.xilinx.com/v/u/en-US/pg374-dfx-controller
[24] LogiCORE IP AXI HWICAP (v2.03.a) Data Sheet (AXI)(DS817), 2012, [Online; accessed 30-May-2023]. [Online]. Available: https://docs.xilinx.com/v/u/en-US/ds817_axi_hwicap
[25] Xilinx, “Vivado design suite user guide: Partial reconfiguration v2020.1,” 2020, [Online; accessed 30-May-2023]. [Online]. Available: https://docs.xilinx.com/v/u/2020.1-English/ug909-vivado-partial-reconfiguration
[26] Vivado Design Suite User Guide: Dynamic Function eXchange (UG909), 2023, [Online; accessed 30-May-2023]. [Online]. Available: https://docs.xilinx.com/r/en-US/ug909-vivado-partial-reconfiguration/Introduction
[27] A. Moradi, A. Barenghi, T. Kasper, and C. Paar, “On the vulnerability of fpga bitstream encryption against power analysis attacks: Extracting keys from Xilinx virtex-ii fpgas,” in Proceedings of the 18th ACM Conference on Computer and Communications Security, ser. CCS ’11. New York, NY, USA: Association for Computing Machinery, 2011, p. 111–124. [Online]. Available: https://doi.org/10.1145/2046707.2046722
[28] M. Ender, A. Moradi, and C. Paar, “The unpatchable silicon: A full break of the bitstream encryption of xilinx 7-series {FPGAs},” in 29th USENIX Security Symposium (USENIX Security 20), 2020, pp. 1803–1819.
[29] Xilinx, “Solution zynqmp pl programming,” 2022, [Online; accessed 30-May-2023]. [Online]. Available: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841847/Solution+ZynqMP+PL+Programming
[30] ——, “Xapp1323(v1.1) developing tamper-resistant designs with zynq ultrascale+ devices application note,” 2018, [Online; accessed 30-May-2023]. [Online]. Available: https://docs.xilinx.com/v/u/en-US/xapp1323-zynq-usp-tamper-resistant-designs
[31] G.-Y. Chang and C.-A. Lu, “Trustfure: A tamper resistance system for software defined satellite,” pp. 1–18, 2022.
[32] S. T. Heiko Lohrke, C. B. Thilo Krachenfels, and J.-P. Seifert, “Key extraction using thermal laser stimulation: A case study on xilinx ultrascale {FPGAs},” in IACR Transactions on Cryptographic Hardware and Embedded Systems, 2018.
[33] Xilinx, “Ug585 zynq-7000 soc technical reference manual,” 2021, [Online; accessed 30-May-2023]. [Online]. Available: https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM
指導教授 張貴雲(Guey-Yun Chang) 審核日期 2023-7-28
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明