具自適應迴路增益控制器之 5 Gbps 相位內插式 時脈與資料回復電路

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廖品媗(Pin-Hsuan Liao) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具自適應迴路增益控制器之 5 Gbps 相位內插式時脈與資料回復電路
(A 5 Gbps PI-based Clock and Data Recovery with Adaptive Loop Gain Controller)

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至系統瀏覽論文 (2029-1-19以後開放)

摘要(中)

近年來，隨著半導體產業的迅速發展，產品應用需要更高的資料傳輸頻寬，高速串列傳輸技術成為現在資料傳輸的主流。在串列傳輸系統中，接收端需要使用時脈與資料回復電路來重新調整輸入資料的時脈，以確保正確的資料還原。然而，系統中可能存在各種雜訊和訊號衰減，導致誤碼率上升，因此提升抖動容忍度、減少誤碼率成為時脈與資料回復電路中的設計目標。

本論文根據 USB 3.2 gen 1 規格實現一個具自適應迴路增益控制器之 5 Gbps 相位內插式時脈與資料回復電路。透過觀察相位旋轉器旋轉狀況，自適應迴路增益控制器偵測輸入資料的抖動頻率資訊，切換資料回復迴路的迴路增益，以達到在不同的抖動頻率下，優化系統的產生的抖動，提升整體電路的抖動容忍度，降低誤碼率。自適應迴路增益改善了 132% 的低頻抖動容忍度和 17% 高頻抖動容忍度。本論文使用用 TSMC 90 nm (TN90GUTM) 1P9M CMOS 製程來實現，電路操作電壓為 1 V，晶片面積為 1.49 mm2，核心電路面積為 0.066 mm2，輸入資料速率為 5 Gbps 時，還原時脈的峰對峰值抖動為 14.7 pspp，方均根值抖動為 3.46 psrms，消耗功率為 31.04 mW。

摘要(英)

In recent years, with the rapid development of the semiconductor industry, products require higher data transmission bandwidth, and high-speed serial transmission technology has become the mainstream for data transmission. In serial transmission systems, the RX needs to use clock and data recovery circuits (CDR) to readjust the input data clock to ensure accurate data recovery. However, various noise and signal attenuation may exist in the system, leading to an increase in error rates. Therefore, improving jitter tolerance (JTOL) and reducing Bit-Error-Rate (BER) have become design goals in clock and data recovery circuits.

This paper presents the implementation of a 5 Gbps phase-interpolator based clock and data recovery circuit with an adaptive loop gain controller (ALGC) based on the USB 3.2 Gen 1 specification.The adaptive loop gain controller detects the jitter frequency information of the input data, switches the loop gain of the data recovery loop, and optimizes JTOL under different jitter frequencies. This enhances the overall circuit′s jitter tolerance and reduces error rates. The adaptive loop gain improves low-frequency jitter tolerance by 132% and high-frequency jitter tolerance by 17%. The circuit is implemented using the TSMC 90 nm (TN90GUTM) 1P9M CMOS process, operates at 1 V, with a chip area of 1.49 mm², a core circuit area of 0.066 mm². At a data rate of 5 Gbps, the peak-to-peak jitter of the recovered clock is 14.7 pspp, the root mean square jitter is 3.46 psrms, and the power consumption is 31.04 mW.

關鍵字(中)

★ 時脈與資料回復電路
★ 抖動容忍度

關鍵字(英)

★ Clock and Data Recovery
★ CDR
★ Jitter tolerance

論文目次

摘要 i
Abstract ii
目錄 iii
圖目錄 vi
表目錄 xi
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 3
第2章高速串列傳輸之訊號完整性 4
2.1 隨機二位元資料 4
2.1.1 資料型態 4
2.1.2 資料特性 5
2.1.3 資料編碼形式 6
2.2 抖動介紹 7
2.2.1 定量性抖動 (Deterministic Jitter, DJ) 8
2.2.2 隨機性抖動 (Random Jitter, RJ) 11
2.3 抖動量測方法 12
2.3.1 時間間隔誤差 (Time Interval Error, TIE) 13
2.3.2 週期抖動 (Period Jitter) 13
2.3.3 循環抖動 (Cycle-to-Cycle Jitter) 13
2.4 眼圖分析 14
2.5 誤碼率 (Bit Error Rate, BER) 15
第3章時脈與資料回復電路背景介紹 18
3.1 時脈與資料回復電路簡介 18
3.1.1 相位偵測器型態 19
3.1.2 相位偵測器取樣速率 20
3.1.3 抖動容忍度 (Jitter Tolerance, JTOL) 21
3.1.4 抖動轉移函數 (Jitter Transfer, JTF) 22
3.2 時脈與資料回復電路相關設計 23
3.2.1 鎖相迴路式時脈與資料回復電路 (PLL-based CDR) 23
3.2.2 混合鎖相迴路及延遲鎖相迴路式時脈與資料回復電路 (D/PLL CDR) 24
3.2.3 突發模式時脈與資料回復電路 (Burst mode CDR) 25
3.2.4 超取樣式時脈與資料回復電路 (Oversampling CDR) 26
3.2.5 相位內插器式時脈與資料回復電路 27
3.3 自適應時脈與資料回復電路相關設計 28
3.3.1 自適應解析度控制之相位內插式時脈與資料回復電路 28
3.3.2 自適應迴路頻寬之相位內插式時脈與資料回復電路 29
3.3.3 自適應迴路增益之時脈與資料回復電路 30
3.4 比較與討論 31
第4章具自適應迴路增益控制器之相位內插式時脈與資料回復電路設計與實現 33
4.1 電路架構 33
4.2 鎖相迴路 35
4.2.1 鎖相迴路系統分析 36
4.2.2 相位頻率偵測器 (Phase Frequency Detector, PFD) 38
4.2.3 充電幫浦 (Charge Pump, CP) 40
4.2.4 壓控震盪器 (Voltage Controlled Oscillator, VCO) 41
4.2.5 除頻器(Divider) 43
4.3 資料回復迴路 44
4.3.1 資料回復迴路系統分析 45
摘要 i
Abstract ii
目錄 iii
圖目錄 vi
表目錄 xi
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 3
第2章高速串列傳輸之訊號完整性 4
2.1 隨機二位元資料 4
2.1.1 資料型態 4
2.1.2 資料特性 5
2.1.3 資料編碼形式 6
2.2 抖動介紹 7
2.2.1 定量性抖動 (Deterministic Jitter, DJ) 8
2.2.2 隨機性抖動 (Random Jitter, RJ) 11
2.3 抖動量測方法 12
2.3.1 時間間隔誤差 (Time Interval Error, TIE) 13
2.3.2 週期抖動 (Period Jitter) 13
2.3.3 循環抖動 (Cycle-to-Cycle Jitter) 13
2.4 眼圖分析 14
2.5 誤碼率 (Bit Error Rate, BER) 15
第3章時脈與資料回復電路背景介紹 18
3.1 時脈與資料回復電路簡介 18
3.1.1 相位偵測器型態 19
3.1.2 相位偵測器取樣速率 20
3.1.3 抖動容忍度 (Jitter Tolerance, JTOL) 21
3.1.4 抖動轉移函數 (Jitter Transfer, JTF) 22
3.2 時脈與資料回復電路相關設計 23
3.2.1 鎖相迴路式時脈與資料回復電路 (PLL-based CDR) 23
3.2.2 混合鎖相迴路及延遲鎖相迴路式時脈與資料回復電路 (D/PLL CDR) 24
3.2.3 突發模式時脈與資料回復電路 (Burst mode CDR) 25
3.2.4 超取樣式時脈與資料回復電路 (Oversampling CDR) 26
3.2.5 相位內插器式時脈與資料回復電路 27
3.3 自適應時脈與資料回復電路相關設計 28
3.3.1 自適應解析度控制之相位內插式時脈與資料回復電路 28
3.3.2 自適應迴路頻寬之相位內插式時脈與資料回復電路 29
3.3.3 自適應迴路增益之時脈與資料回復電路 30
3.4 比較與討論 31
第4章具自適應迴路增益控制器之相位內插式時脈與資料回復電路設計與實現 33
4.1 電路架構 33
4.2 鎖相迴路 35
4.2.1 鎖相迴路系統分析 36
4.2.2 相位頻率偵測器 (Phase Frequency Detector, PFD) 38
4.2.3 充電幫浦 (Charge Pump, CP) 40
4.2.4 壓控震盪器 (Voltage Controlled Oscillator, VCO) 41
4.2.5 除頻器(Divider) 43
4.3 資料回復迴路 44
4.3.1 資料回復迴路系統分析 45
4.3.2 自適應迴路增益技術操作說明 47
4.3.3 自適應迴路增益控制器 (Adaptive Loop Gain Controller, ALGC) 50
4.3.4 二進位相位偵測器 (Bang-bang Phase Detector, BBPD) 52
4.3.5 解串列器/多數投票機制電路 (Deserializer/Majority Voter, Des/MV) 54
4.3.6 相位旋轉器 (Phase Rotator, PR) 56
4.3.7 相位選擇器 (Phase Selector, PS) 57
4.3.8 相位內插器 (Phase Interpolator, PI) 58
4.4 模擬結果 59
4.4.1 佈局前模擬 60
4.4.2 佈局後模擬 63
第5章晶片佈局與量測 67
5.1 電路佈局 67
5.1.1 晶片封裝 68
5.1.2 晶片電源佈局與規劃 70
5.2 量測考量 71
5.2.1 量測環境 71
5.2.2 低頻輸入緩衝器 72
5.2.3 高頻輸入緩衝器 73
5.2.4 高頻輸出緩衝器 74
5.3 規格比較表 75
第6章結論 77
6.1 結論 77
6.2 未來研究方向 78
參考文獻 79

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2024-1-22

推文