結合共軛梯度法與雅可比法之軟性輸出的巨量多輸入多輸出偵測器設計

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姓名

羅頡(Lo-Chieh) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

結合共軛梯度法與雅可比法之軟性輸出的巨量多輸入多輸出偵測器設計
(A Design of Soft-output MMSE Detector with Joint Conjugate Gradient Jacobi for Massive MIMO Systems)

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至系統瀏覽論文 (2026-8-1以後開放)

摘要(中)

近代科技以爆炸性的速度在成長，發展出了如人工智慧(Artificial Intelligence)、5G網路(fifth Generation Mobile Networks)等等，而這些技術的資料傳輸量又更高了一些，多輸入多輸出系統已經漸漸無法負荷，於是又將天線數量向上提升形成了巨量多輸出多輸入系統(Massive MIMO system)，常見的天線數有64x8、128x8 (N_r×N_t) 等等，而本論文嘗試以較為困難的128x32的天線數量進行實現，在計算最小均方誤差演算法(Minimum Mean Square Error)時，演算法中的反矩陣複雜度為O(N_t^3)，故本論文以共軛梯度雅可必法(Joint Conjugate Gradient Jacobi Method)去逼近MMSE中的反矩陣，此演算法前面以共軛梯度法進行迭代後面以雅可比法進行收尾，因共軛梯度法能提供較好的收斂性，所以以它先搜尋正確的方向，後面再以複雜度較低的雅可比法進行迭代，雅可比法是透過對角矩陣和剩餘矩陣進行迭代的演算法，因Massive MIMO有著對角優勢，雅可比法的迭代也能降低系統的位元錯誤率(Bit Error Rate)，所以將兩種演算法結合之後，獲得的位元錯誤率幾乎等同於所要逼近的演算法MMSE。
而在電路架構上為了運算格拉姆矩陣(Gram matrix)，將通道矩陣分為四等分並利用格拉姆矩陣的共軛性與對稱性進行平行處理最後相加以獲得更高的吞吐量(throughput)，整體的電路架構以管線化(pipeline)進行設計，將其分為三個stage進行運算，晶片時做採用的是TSMC的40nm製程，核心面積為3.72mm^2，操作頻率約423MHz，功耗約為877mW，傳輸量可以達到768Mbps的速度。

摘要(英)

Modern technology is growing at an explosive rate, that developed such as AI(artificial intelligence),5G network(fifth Generation Mobile Network),etc. The data throughput of these technologies is a bit higher, MIMO systems have been gradually unable to load. Therefore, the number of antennas is increased to form a Massive MIMO system. Common antenna numbers are 64x8、128x8 and so on. However, this paper tries to implement it with the more difficult number of antennas which is 128x32. When calculating the MMSE (Minimum Mean Square Error), the complexity of the inverse matrix in the algorithm is O(N_t^3). Therefore, this paper uses the Joint Conjugate Gradient Jacobi algorithm to approximate the inverse matrix in MMSE. This algorithm uses conjugate gradient method to iterate before and ends with the Jacobi method. Because the CG method can provide better convergence, so use it to search the correct direction first. Later, iterate with the less complex Jacobi method. The Jacobi method is an iterative algorithm through the diagonal matrix and residual matrix. Because Massive MIMO has diagonal advantage, the iteration of the Jacobi method can also reduce the BER(Bit Error Rate) of the system.
In the circuit architecture, in order to operate the Gram matrix, this paper divides the channel matrix into quarters and use the conjugation and symmetry of the Gram matrix for parallel processing and finally sum to obtain higher throughput. The overall circuit architecture is designed with pipeline and divided into three stages for operation. The chip design is implemented in TSMC 40 nm CMOS technology. The core area is 3.72 mm^2,maximum frequency is 423MHz, dynamic power consumption is 877mW, throughput can achieve 768Mbps.

關鍵字(中)

★ 多輸入多輸出天線系統

關鍵字(英)

★ MIMO system

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 viii
表目錄 xi
第一章緒論 1
1.1 背景 1
1.2 研究動機 2
1.3 論文貢獻 3
第二章巨量多輸入多輸出天線系統(Massive MIMO System) 4
2.1 巨量多輸入多輸出天線系統介紹 4
2.2 巨量多輸入多輸出天線系統架構 4
2.3 偵測演算法 5
2.3.1 非線性偵測演算法 5
2.3.2 線性偵測演算法 6
2.3.3 最小均方誤差 (Minimum Mean Square Error) 6
2.4 對角優勢矩陣 10
2.5 通道硬化 11
第三章近似法 12
3.1 最小均方誤差法的優缺點 12
3.2 諾伊曼級數(Neumann) 13
3.3 雅可必法(Jacobi method) 14
3.4 Krylov子空間法(Krylov subspace method) 16
3.4.1 共軛梯度法 (Conjugate Gradient Method) 17
3.4.2 共軛剩餘法(Conjugate Residual) 22
3.5 最深梯度下降雅可比法(Joint Steepest Descent and Jacobi method) 23
3.6 共軛梯度雅可比法(Joint Conjugate Gradient and Jacobi method) 24
第四章系統模擬 27
4.1 系統架構 27
4.2 迴旋碼編碼器(Convolutional encoder) 28
4.3 維特比解碼器(Viterbi decoder) 29
4.4 對數似然比(Log-likelihood ratio) 30
4.5 訊擾雜比(Signal to Interference plus Noise Ratio) 34
4.6 模擬結果 36
第五章硬體架構設計 38
5.1 硬體設計流程 38
5.2 硬體電路輸出入介紹 40
5.3 基本電路介紹 41
5.3.1 電路第一級(STAGE1) 42
5.3.1.1 格拉姆矩陣(Gram matrix) 42
5.3.1.2 b處理電路 47
5.3.1.3 CORDIC 倒數電路 48
5.3.1.4 x0 處理電路 52
5.3.1.5 g0 處理電路 53
5.3.1.6 第一級電路總架構 55
5.3.2 電路第二級(stage2) 57
5.3.2.1 p0Ap0 和 g0g0 處理電路 57
5.3.2.2 第二級電路總架構 60
5.3.3 電路第三級(stage3) 62
5.3.3.1 CG和殘差處理電路 62
5.3.3.2 JC處理電路 64
5.3.3.3 第三級電路總架構 67
5.3.4 Memory Block 68
5.4 測試資料記憶體電路 70
5.4.1 測試資料記憶體電路系統 70
5.4.2 測試資料記憶體電路介紹 71
5.4.3 測試資料記憶體 72
5.4.4 測試資料記憶體電路控制 : 輸入H 73
5.4.5 測試資料記憶體電路時序 : 輸入H 76
5.4.6 測試資料記憶體電路控制 : 輸入y 77
5.4.7 測試資料記憶體電路時序 : 輸入y 79
5.4.8 測試資料記憶體電路合成結果 79
5.4.9 加入測試資料記憶體電路後的電路輸出入腳位 80
5.5 定點數模擬分析 80
5.6 模擬驗證 81
第六章晶片設計結果 83
6.1 錯誤覆蓋率 84
6.2 布局圖 85
6.3 核心電路分布圖 87
6.4 核心電路面積功耗分布 89
6.5 晶片規格 91
第七章結論與未來展望 95
第八章參考文獻 96

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指導教授

薛木添(Muh-Tian Shiue)

審核日期

2024-1-22

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