二維半導體元件模擬的電流和電場分析

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姓名

趙明達(Ming-Ta Chao) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

二維半導體元件模擬的電流和電場分析
(Current-flow and Electric-field Analysis in 2-D Semiconductor Device Simulation)

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摘要(中)

中文摘要
本篇論文一開始主要是討論在二維的半導體元件模擬器中開發出一套向量繪圖(vector-plot)的方法。此向量繪圖的技術能提供我們去了解半導體元件內部的電流及電場的分佈情形。透過所畫出的箭頭, 我們可以很清楚的表示出電流及電場的大小和方向。其次，我們將提出一些模型(model)去探討金氧半電晶體(MOSFET)內部的非理想情況, 在本論文內所討論的非理想狀況包含場相關的遷移率(field-dependent mobility)，氧化層內的固定電荷(fixed charge in the oxide layer)。最後我們提出一個元素切割方法(element-cut method)去模擬BJT元件。元素切割方法中的二分切線(bisection lines)能夠幫助我們去計算BJT元件內部的電流分量。透過此元素切割方法，我們能解釋內部(internal) BJT的電流增益(current gain)大於合併(combined) BJT的電流增益之原因。

摘要(英)

ABSTRACT
In this thesis, first we develop a vector-plot tool for 2-D device simulator. The vector-plot development technique can provide us to understand the distribution of the current flow and electric field inside the device. By the plot of the arrow, it is clear to show the magnitude and the direction of the current flow and electric field. Secondly, we will propose the model to discuss the nonideal cases of the MOSFET device. The nonideal cases are field-dependent mobility, fixed charge in the oxide layer in this thesis. Finally, we propose the element-cut method in the BJT device simulation. The bisection lines of the element-cut method can help us to calculate the current component inside the BJT device. We can explain that the current gain of the internal BJT is larger than the combined BJT by the element-cut method.

關鍵字(中)

★ 半導體元件模擬電流和電場分析

關鍵字(英)

★ current-flow and electric-field analysis

論文目次

Contents
1. Introduction 1
2. Vector-Plot Development For 2-D Device Simulation 3
2.1 2-D Equivalent Circuit Model……………………………………….3
2.2 Vector-Plot Development……………………………………………5
2.2.1 Coordinate Transform………………………………………………..7
2.2.2 Grid Plot for 2-D device……………………………………………….8
2.2.3 Current and Field Calculation in a Mesh………………………………9
2.2.4 Vector Scaling………..………………………………………………10
2.3 Simulation of the Vector-Plot in PN Diode………………………...12
2.3.1 Simulation example of the PN Diode………………………………...12
2.3.2 Discussion……………………………………………………………15
2.4 Simulation of the Vector-Plot in MOS Device…………………….18
2.4.1 Simulation example of the MOS Device……………………………..18
2.4.2 Discussion……………………………………………………………21
2.5 Summary………………………………………………………………...23
3. Current and Field Investigation in MOSFET 24
3.1 Impact of the MOSFET Electric Fields on Mobility…………….24
3.1.1 Effect of the Transverse and Longitudinal Electric Field………..24
3.1.2 Field-Dependent Mobility Model…………………………………25
3.1.3 Simulation Result and Discussion………….………………………..26
3.2 Nonideal Disorder of the oxide layer in the MOS device…..28
3.2.1 Effect of Fixed Charge Within Oxide Layer………………………...29
3.2.2 The 2-D Modeling of Fixed Charge within oxide layer……….…….34
3.2.3 Simulation Result and Discussion…………….……………………..36
4. Current-Flow Application in BJT Simulation 39
4.1 The Principle of the Parasitic BJT in 2-D BJT Simulation……….39
4.2 The Element-Cut Methods……………………………………………41
4.3 Simulation Result and Discussion……………………………………44
5. Conclusion 46

參考文獻

Reference
[1] H. C. Casey, Devices For Integrated Circuit, Chapter 7, John Wiley & Sons Inc., 1999.
[2] H. C. Casey, Devices For Integrated Circuit, Chapter 8, John Wiley & Sons Inc., 1999.
[3] E. S.Yang, Microelectronic Devices, Chapter 5, McGraw-Hill, 1988.
[4] E. S.Yang, Microelectronic Devices, Chapter 9, McGraw-Hill, 1988.
[5] E. S.Yang, Microelectronic Devices, Chapter 10, McGraw-Hill, 1988.
[6] E. S.Yang, Microelectronic Devices, Chapter 11, McGraw-Hill, 1988.
[7] S. Wolf, Silicon Processing for the VLSI Era (Volume 3-The submicron MOSFET), Chapter 5, Lattice Press, 1995
[8] C. L. Teng, “An equivalent circuit approach to mixed-level device and circuit simulation,” M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, Jun. 1997.
[9] Z. C. Liu, “Comparison of two potential variables in mixed-level device and circuit simulation,” M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, Jun. 1998.
[10] C. C. Chang, “Verification of 1D BJT numerical simulation and its application to mixed-level device and circuit simulation,” M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, Jun. 2001.
[11] C.-C. Chang, J.-F. Dai, and Y.-T. Tsai, ”Verification of 1D BJT numerical simulation and its application to mixed-level device and circuit simulation,” Int. J. of Numerical Modelling:Electronic Networks. Devices and Fields, pp. 81-94, 2003.
[12] S. J. Li, “An equivalent circuit of impact-ionization and its applications on semiconductor devices,” M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, Jun. 2002.
[13] S. Selberherr, Analysis and Simulation of Semiconductor Devices. New York: Springer, 1984.

指導教授

蔡曜聰(Yao-Tsung Tsai)

審核日期

2003-6-20

推文