抑制同步切換雜訊之高速傳輸器

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：129

、訪客IP：3.142.42.32

姓名

黃伯任(Po-Jen Huang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

抑制同步切換雜訊之高速傳輸器
(The high-speed transmitter for simultaneous switching noise rejection)

相關論文

★ 運算放大器之自動化設計流程及行為模型研究	★ 匯流排上的時間延遲及交談失真的偵錯設計技巧
★ 適用於自動測試機台的時間產生器	★ 混波測試匯流排的量測學
★ 高速連結之時序與資料回復	★ 基於IEEE 1057之類比數位轉換器量測技術
★ 應用於高畫質電視之載波回復電路架構	★ 單晶片測試機之前端驅動電路設計
★ 系統晶片類比數位轉換器測試之數位信號處理程式庫	★ A 2.5V,0.35um,2.5Gbps 傳送接收器設計
★ 內建式類比數位/數位類比轉換器線性度之自我測試	★ 高準確度及低成本之電壓量測技術
★ 應用於ATSC VSB時脈回復之全數位延遲線迴路	★ 適用於晶片間通訊之高速傳輸介面
★ 內建式類比數位轉換器之自我校正方法	★ 高速序列傳輸之量測技術

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

在此論文中，我們主要的研究主題是探討同步切換雜訊對訊號完整性的影響，並進而去降低雜訊的量。首先，我們將簡單的說明及討論通道建模、介面電路的雜訊來源及低電壓差動訊號標準，並簡介造成同步切換雜訊的相關因素和過去一般用來降低此雜訊的機制。根據這些知識，我們提出了輸出驅動器的電晶體順序導通的方法，藉由電流非同時流到接地端的打線來有效的降低同步切換雜訊。接著，我們利用這個原理，應用在一個符合AGTL標準的2Gbps收發器，及一個符合低電壓差動訊號標準的5Gbps收發器。此外，在不使用電流源的情況下，我們亦可以大幅的降低電晶體的尺寸及花費。並在電路內加上一個編碼器，讓電路在製程漂移的情況下，輸出的電壓準位還能維持在一定電壓範圍。
論文中，我們將實現一個符合AGTL標準的2Gbps的傳送器。此傳送器是使用tsmc018的製程且在1.8V的供應電壓下可以操作在2Gbps，另外晶片面積則為1.5x1.5mm2，模擬結果可以讓同步切換雜訊抑制在原有雜訊的一半以內。另外我們亦模擬一個符合低電壓差動訊號標準的5Gbps收發器，將同步切換雜訊抑制在50mV左右。透過這些處理，我們可以不使用電流源而有效的抑制雜訊的量，並讓輸出訊號能維持在標準的電壓準位。

摘要(英)

In this thesis, our major topic is to discuss the effect of simultaneous switching noise (SSN) on signal integrity and to reduce the noise magnitude. First, we will study the channel modeling, signaling noise sources and low voltage differential signaling (LVDS) standard. We also briefly introduce the factors which causes SSN and some mechanisms to reduce the noise in the past. Basing on these considerations, we propose the orderly turn-on method of the output driver, and we apply this method in a 2Gbps transceiver of the assisted gunning transceiver logic (AGTL) standard and a 5Gbps transceiver of the LVDS standard. Without using the current source, we can further reduce the transistor size and the cost. We also invent a decoder to control the voltage level against the process variation.
A 2Gbps transmitter has been implemented in this thesis. It is compatible with the AGTL standard. Fabricated in a TSMC 0.18-um CMOS technology, the transmitter circuit operates at 2Gbps with a 1.8V power supply and the chip area is 1.5x1.5mm2. It has been approved for fabrication by the Chip Implementation Center (CIC). The simulation result shows that the SSN effects have been reduced to half of the original ones. Furthermore, we also simulate a 5Gbps transceiver of the LVDS standard and the SSN effect has been reduced to 70mV. By these methods, we can reduce the SSN effect and maintain the voltage level of output signal without using any current source.

關鍵字(中)

★ 同步切換雜訊
★ 低電壓差動訊號
★ 輸出驅動器

關鍵字(英)

★ SSN
★ AGTL
★ LVDS
★ transmitter

論文目次

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Research Direction 2
1.3 Thesis Organization 3
Chapter 2 Overview of Simultaneous Switch Noise Effect and Reduction 4
2.1 Introduction of High-Speed Serial Link 5
2.1.1 Transmission Line model 8
2.2 Noise Source 9
2.2.1 Signaling Noise Sources 9
2.2.2 Switching Noise Mechanism and Theory 11
2.2.3 Simultaneous Switching Noise Phenomena 15
2.3 Introduction of SSN Reduction 15
2.3.1 Optimal Rise/Fall Time 16
2.3.2 Reducing Inductance 17
2.3.3 Large Ratio of Supply to Signal Connections 17
2.3.4 Reduce Signal Swing and Use Differential Drivers 18
2.3.5 Separate Power Supply Network 18
2.3.6 Decoupling Capacitors 19
2.4 Introduction of the New Approach to SSN Rejection 19
2.5 Summary 21
Chapter 3 SSN Rejection for AGTL Implementation 22
3.1 Introduction of AGTL 23
3.1.1 GTL 23
3.1.2 AGTL 25
3.2 System Architecture 26
3.3 Transmitter Functional Blocks 27
3.3.1 Generation of Random Data 27
3.3.2 Ring Oscillator 29
3.3.3 AGTL Driver Design 29
3.3.4 Pre-driver Design 32
3.3.5 RC delay Design 33
3.4 Transmitter Simulation Result 34
3.5 Summary 40
Chapter 4 SSN Rejection for LVDS Implementation 41
4.1 Introduction of LVDS 42
4.1.1 LVDS 42
4.2 System Architecture 46
4.3 Functional Blocks of Transmitter 48
4.3.1 LVDS Driver design 48
4.3.2 Pre-Driver design with duty cycle control 50
4.3.3 RC delay element and decoder 51
4.4 Transmitter Simulation Result 52
4.5 The Advantage of Proposed driver and Compare 58
4.6 Summary 62
Chapter 5 Conclusion 63
Bibliography 64

參考文獻

[1] Novak, I. , “Reducing simultaneous switching noise and EMI on ground/power planes by dissipative edge termination, “ Electrical Performance of Electronic Packaging, 1998. IEEE 7th topical Meeting on , 26-28 Oct 1998
[2] R. Senthinathan and R.Yach., “High-speed 1 output driver design methodology, ” Intel Corporation: Technical Report, Sept 1988.
[3] R. Senthinathan and J. L. Prince, “Simultaneous switching ground noise calculation for packaged CMOS devices, ” IEEE J. Solid-State Circuits, vol. 26, p. 1724, Nov.1991
[4] C.K. Ken Yang ,“Design of High-Speed Serial Links in CMOS,” Ph.D. Dissertation, Stanford University, 1998.
[5] H. Johnson, M. Graham, “High-Speed Digital Design --- A handbook of black magic,” Prentice-Hall, Inc. 1993.
[6] J. Poulton, et al., “Signaling in high-performance memory systems,” International Solid-State Circuits Conference, tutorial., 1999.
[7] H.B. Bakoglu, “Circuits, Interconnections and Packaging for VLSI,” Addison-Wesley Publishing Company, Inc. 1990.
[8] J. Poulton, et al., “A Tracking Clock Recovery Receiver for 4 Gb/s Signaling,” IEEE Micro, 1998.
[9] W.J. Dally and J. Poulton , “Transmitter equalization for 4Gb/s signaling,” IEEE Micro, 1997.
[10] R. Farjad-Rad, C. K. K. Yang, M. A. Horowitz, and T. H. Lee, “A 0.4 um CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter,” IEEE J. Solid-State Circuits,May 1999.
[11] A. Fiedler, et al., “A 1.0625 Gbps transceiver with 2X Oversampling and transmit pre-emphasis,” IEEE International Solid-State Circuits Conference. Digest of Technical Papers, pp. 238-239, Feb 1997.
[12] Star-HSPICE User’s Manual , Avant! Corporation, 2001.
[13] J.M. Khoury and K.R. Lakshmikumar., “High-Speed Serial Transceivers for Data Communication Systems,” IEEE Communications Magazine, July 2001
[14] M.E. Lee, “An Efficient I/O and Clock Recovery Design For Terabit Integrated Circuits,” Ph.D. Dissertation, Stanford University, August 2001.
[15] S.H. Hall, G.W. Hall, et al. , “High-Speed Digital System Design—A handbook of interconnect theory and design practices,” Wiley-Interscience Publication, 2000.
[16] B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill Companies, Inc., 2001.
[17] TUMMALA, R.R., RYMASZEWSKI, E.J., and KLOPFENSTEIN, A.G.: “Microelectronics packaging handbook,” Chapman & Hall, New York, 1997.
[18] BAKOGLU, H.B.: “Circuits, interconnections, and packaging for VLSI,” Addison-Wesley, Reading, Massachusetts, 1990, p.303
[19] Gong, S.; Hentzell, H.; Persson, S.-T.; Hesselborn, H.; Lofstedt, B.; Hansen, M. “Packaging impact on switching noise in high-speed digital systems, “ Circuits, Devices and Systems, IEE Proceedings- , Volume: 145 Issue: 6 , Dec 1998
[20] SENTHINATHAN, R., and PRINCE, J.L.: “Simultaneous switching ground noise calculation for packaged CMOS device, “ IEEE J. Solid-State Circuit, 1991, 26, (11), pp.1724-1728
[21] Ammar, R.; Ajouri, C.: “GTL: a low-swing solution for high-speed digital logic, “WESCON/'95. Conference record. 'Microelectronics Communications Technology Producing Quality Products Mobile and Portable Power Emerging Technologies' , 7-9 Nov 1995
[22] The datasheet of Intel Pentium 4 Processor in the 423-pin Package
[23] B. Razavi, “Design of Integrity Circuit for Optical Communications,” McGraw-Hill Companies, Inc., 2002
[24] “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits,” ANSI/TIA/EIA-644-1995, Telecommunications Industry Association, Nov. 15, 1995.
[25] “IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI),” IEEE Std 1596.3-1996, IEEE Computer Society, July 31, 1996.
[26] LVDS Owner’s Manual , Corporation, 2000.

指導教授

劉建男、蘇朝琴
(Chien-Nan Liu、Chauchin Su)

審核日期

2003-7-8

推文