以單一複製延遲單元實現次諧波注入時序校正之注入式鎖相迴路

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姓名

詹宜庭(Yi-Ting Chan) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

以單一複製延遲單元實現次諧波注入時序校正之注入式鎖相迴路
(An Injection-locked Phase-locked Loop with Single Replica Delay Cell Sub-Harmonically Injection Timing Calibration)

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至系統瀏覽論文 (2027-7-31以後開放)

摘要(中)

鎖相迴路用於產生高品質的時脈訊號，而加入次諧波注入技術將具有抑制振盪器高頻相位雜訊的特性，但是也同時面臨若注入時序不佳將嚴重影響電路效能的問題將造成參考突波 (Reference spur)及時脈抖動 (Jitter)的惡化。因此本論文提出操作於2.4GHz以單一複製延遲單元實現次諧波注入時序校正之注入式鎖相迴路具有額外的迴路自適應校正注入時序到最佳注入位置。並複製環形振盪器中的延遲單元，在校正過程中，以此單級複製延遲單元和注入脈波進行相位比較。區隔了受到注入及進行相位比較的延遲單
元。額外耗費少量的功率消耗及硬體面積便能達到更準確的注入位置，提升電路效能。電路設計與佈局以90nm CMOS製程實現。輸出時脈頻率為2.4GHz、參考時脈訊號為150MHz。完成次諧波注入時序校正後，次諧波注入式鎖相迴的參考突波為-44.3dBc輸出相位雜訊下為-115.0dBc/Hz @ 1MHz offset；方均跟抖動為970fs；不含輸入與輸出緩衝器的電路功率消耗為7.3mW核心電路面積為0.063 mm2，晶片面積為0.912 mm2。

摘要(英)

Phase-locked loop (PLL) is used to generate high-quality clock signals, and incorporating sub-harmonic injection technology will have the characteristic of suppressing high-frequency phase noise of the oscillator. However, it also faces the problem of severely affecting circuit performance if the injection timing is poor, such as degradation in metrics like Reference spur and Jitter. Therefore, this paper proposes an injection-locked phase-locked loop with single replica delay cell sub-harmonically injection timing calibration operating at 2.4GHz, featuring additional loop-adaptive calibration to optimize injection timing to the best position. It duplicates delay units within the ring oscillator, and during the calibration process, it compares phases with this single replica delay cell and injection pulse. This segregates the delay cells affected by injection and those used for phase comparison. Achieving a more accurate injection position requires only a small additional power consumption and hardware area, thereby enhancing circuit performance.
The circuit design and layout are implemented using a 90 nm CMOS process. The output clock frequency is 2.4GHz, and the reference clock signal is 150MHz. After completing the sub-harmonically injection timing calibration, the reference spur of the sub-harmonic injection-locked loop is -44.3 dBc; output phase noise is -115.0 dBc/Hz @ 1MHz offset; root mean square (RMS) jitter is 970fs; circuit power consumption without input and output buffers is 7.3 mW; core circuit area is 0.063 mm2, and the chip area is 0.912 mm2.

關鍵字(中)

★ 鎖相迴路
★ 次諧波注入技術
★ 次諧波注入式鎖相迴路
★ 注入時序校正
★ 單一複製延遲單元
★ 環形振盪器

關鍵字(英)

★ Phase-Locked Loop
★ Sub-harmonically Injection locked
★ Sub-harmonically Injection locked PLL
★ Injection Timing Calibration
★ Single Replica Delay Cell
★ Ring-based Oscillator

論文目次

摘要 vi
Abstract vii
致謝 viii
目錄 ix
圖目錄 xii
表目錄 xv
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 2
第2章次諧波注入式鎖相迴路先前技術探討 3
2.1 鎖相迴路 (Phase-locked loop, PLL) 3
2.2 相位雜訊 (Phase Noise) 4
2.3 次諧波注入鎖定技術 5
2.3.1 倍頻延遲鎖定迴路 (Multiplying Delay-Locked Loop, MDLL) 5
2.3.2 次諧波注入式振盪器 (Injection-Locked VCO) 6
2.3.3 次諧波注入式鎖相迴路 (Sub-Harmonically Injection-Locked Phase-Locked Loop, SILPLL) 7
2.3.4 相位雜訊分析 8
2.3.5 除數限制 (Divisor Limited) 9
2.3.6 參考突波 (Reference Spur) 11
2.3.7 注入時序 (Injection Timing Issue) 12
2.4 次諧波注入時序自我校正技術先前文獻 13
2.4.1 次諧波注入時序校正技術 (一 ) 13
2.4.2 次諧波注入時序校正技術 (二 ) 15
2.4.3 次諧波注入時序校正技術 (三 ) 17
2.5 單複製延遲單元先前文獻探討 19
2.6 先前文獻總結 20
第3章以單一複製延遲單元實現次諧波注入時序校正之注入式鎖相迴路 21
3.1 電路架構與操作 21
3.2 鎖相迴路操作與設計鎖相迴路操作與設計 22
3.3 次諧波注入時序校正迴路操作次諧波注入時序校正迴路操作 22
3.4 單複製延遲單元的應用單複製延遲單元的應用 24
3.5 電路操作流程電路操作流程 26
3.5.1 步驟一步驟一 : 鎖相迴路鎖相迴路 26
3.5.2 步驟二步驟二 : 注入時序校正迴路注入時序校正迴路 27
3.6 次諧波注入式鎖相迴路之系統分析次諧波注入式鎖相迴路之系統分析 28
第4章研究架構設計與實現研究架構設計與實現 30
4.1 類比式鎖相迴路子電路設計類比式鎖相迴路子電路設計 30
4.1.1 相位頻率偵測器相位頻率偵測器 (Phase Frequency Detector, PFD) 30
4.1.2 電荷幫浦電荷幫浦 (Charge Pump, CPPLL) 32
4.1.3 迴路濾波器迴路濾波器 (Loop Filter, LF) 34
4.1.4 電壓控制振盪器電壓控制振盪器 (Voltage Control Oscillator, VCO) 35
4.1.5 除頻器除頻器 (Divider, DIV) 38
4.1.6 鎖定偵測器鎖定偵測器 (Locked Detector, LD) 39
4.2 複製延遲單元次諧波注入時序自我校正迴路複製延遲單元次諧波注入時序自我校正迴路 41
4.2.1 縫隙相位偵測器縫隙相位偵測器 (Aperture Phase Detector, APD) 41
4.2.2 脈波產生器脈波產生器 (Pulse Generator, PG) 43
4.2.3 電壓控制延遲線電壓控制延遲線 (Voltage Control Delay Line, VCDL) 44
第5章電路模擬結果電路模擬結果 46
5.1 鎖相迴路模擬結果鎖相迴路模擬結果 46
5.1.1 鎖相迴路佈局前模擬結果 (Pre-layout Simulation of PLL) 46
5.1.2 鎖相迴路佈局後模擬結果 (Post-layout Simulation of PLL) 47
5.2 次諧波注入式鎖相迴路模擬結果 49
5.2.1 次諧波注入式鎖相迴路佈局前模擬結果 (Pre-layout Simulation of SILPLL) 51
5.2.2 次諧波注入式鎖相迴路佈局後模擬結果 (Post-layout Simulation of SILPLL) 54
5.3 次諧波注入式鎖相迴路系統模擬 57
5.4 次諧波注入式鎖相迴路功率消耗 58
5.5 電路佈局 58
5.6 晶片量測環境考量 61
5.7 效能比較 64
第6章結論與未來研究方向 66
6.1 結論 66
6.2 未來研究方向 67
參考文獻 68

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2024-7-26

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