堆疊式矽鍺奈米片場效電晶體用於3奈米之先進製程技術

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：98

、訪客IP：3.138.172.222

姓名

鄭雄(Hsiung Cheng) 查詢紙本館藏

畢業系所

機械工程學系

論文名稱

堆疊式矽鍺奈米片場效電晶體用於3奈米之先進製程技術
(Utilizing Stacked SiGe Nanosheets FET in Advanced 3 Nanometer Process Technology)

相關論文

★ 使用實驗計劃法求得印刷電路板微鑽針最佳鑽孔參數	★ 滾針軸承保持架用材料之電鍍氫脆研究
★ 強制氧化及熱機處理對鎂合金AZ91D固相回收製程之研究	★ 滾針軸承保持架圓角修正之有限元素分析
★ 透過乾式蝕刻製作新型鍺全包覆式閘極電晶體元件	★ 窗型球柵陣列構裝翹曲及熱應力分析
★ 冷軋延對ZK60擠製材的拉伸與疲勞性質之影響	★ 熱引伸輔助超塑成形製作機翼整流罩之設計及分析
★ 超塑性鋁合金5083用於機翼前緣整流罩之研究	★ 輕合金輪圈疲勞測試與分析
★ 滾針軸承保持架之有限元分析	★ 鎂合金之晶粒細化與超塑性研究
★ 平板式固態氧化物燃料電池穩態熱應力分析	★ 固態氧化物燃料電池連接板電漿鍍膜特性研究
★ 7XXX系鋁合金添加Sc之顯微組織與機械性質研究	★ 高延性鎂合金之特性及成形性研究

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 (2029-6-3以後開放)

摘要(中)

原子層沉積(Atomic Layer Deposition, ALD)製程已被用於沉積在高介電常數(High-K)材料，例如氧化釔(Y2O3)，其介電常數相對於二氧化矽較高，這表示在相同的電場下，氧化釔能夠儲存更多電荷進而提高其電容值，也因為具備較高的電容值就具有較佳的絕緣效果，因此其適合作為奈米元件之閘極絕緣層。故本研究在實驗中將使用不同氧化物成長於矽基材，並探討其電性及氧化物與基材間的物理特性。最後，利用原子層沉積製程技術來沉積薄膜層用來製作元件的絕緣層，製造出3奈米世代的矽鍺半導體元件。

本研究中展示的元件製造，其涉及的關鍵製程技術是採用低壓化學氣相沉積矽/矽鍺多層磊晶、並使用四甲基氨氫氧化(Tetramethylammonium hydroxide, TMAH)溶液選擇性蝕刻矽鍺層上的矽層並使用氧化釔作為閘極介電層之金屬閘極進行原子層沉積，所製造的通道長度為180 nm 的堆疊式矽鍺奈米片p 型場效應電晶體，透過電性測量確認ION/IOFF 比約為1×105 以及次臨界擺幅為130 mV/dec。此外，由於其高品質的氧化釔閘極介電層，該裝置表現出極小的漏極誘發降低現象。這些設計可以提高通道的閘極可控性和裝置特性。本研究展示了使用矽/矽鍺多層的堆疊式矽鍺奈米片p 場效應電晶體成功開發矽鍺製程選擇性蝕刻以獲得矽鍺奈米片，其堆疊式矽鍺奈米片環繞式閘極場效電晶體滿足超越3 奈米技術節點以及更高要求
之潛力。

摘要(英)

Atomic Layer Deposition (ALD) process has been employed for depositing high-k dielectric materials, such as yttrium oxide (Y2O3). Its dielectric constant is igher than that of silicon dioxide (SiO2), indicating that under the same electric field, yttrium oxide can store more charge, thereby increasing its capacitance. Due to its higher capacitance, it exhibits superior insulating properties, making it suitable as the gate insulating layer for nanoscale devices. In this research, different oxides will be grown on germanium substrates in the experiments, and the electrical properties and physical characteristics between the oxides and the germanium substrate will be discussed. Finally, utilizing the atomic layer deposition process to stack insulating layers for device isolation, aiming to manufacture 3 nanometer generation germanium semiconductor devices.

In this paper, the key process technologies involved in the fabrication of the device include low-pressure chemical vapor deposition for SiGe/Si multilayer epitaxy, using a wet solution of tetramethylammonium hydroxide for the selective etching of silicon layers over silicon germanium layers, and atomic layer deposition of a high-k dielectric material for the gate dielectric of the metal gate. For the manufactured stacked SiGe NS p-GAAFETs with a channel length of 180nm, the ION/IOFF ratio of approximately 1.0 × 105 and a subthreshold swing of 75 mV/dec were validated via electrical measurements. Furthermore, due to the highquality of the Y2O3 gate dielectric, the device exhibited a minimal drain-induced barrier-lowering effect. These designs can enhance the control of the gate over channel and device characteristics.

關鍵字(中)

★ 原子層沉積
★ 高介電常數
★ 四甲基氨氫氧化合物
★ 金屬閘極

關鍵字(英)

★ Atomic Layer Deposition
★ High-K
★ Tetramethylammonium hydroxide
★ Metal gate

論文目次

目錄
摘要........................................................................i
Abstract...................................................................iii
致謝.......................................................................v
圖目錄......................................................................ix
表目錄......................................................................xii

第一章緒論..................................................................1
1–1 前言.....................................................................1
1–2 研究動機.................................................................3

第二章文獻回顧...............................................................7
2–1 矽/矽鍺多層薄膜沉積........................................................7
2–1–1 化學氣相沉積(Chemical vapor deposition, CVD).............................8
2–1–2 薄膜沉積原理............................................................11
2–1–3 矽/矽鍺多層薄膜介紹及應用 ...............................................13
2–2 電晶體的閘極氧化層選擇與應用 ...............................................19
2–3 物理氣相沉積(Physical vapor deposition, PVD)技術 ..........................27
2–4 原子層沉積(Atomic Layer Deposition, ALD)技術...............................28
2–4–1 原子層沉積原理 ..........................................................30
2–5 元件微縮的短通道效應(Short-channel effect)..................................34

第三章實驗設置與步驟...........................................................40
3–1 實驗流程 ..................................................................40
3–2 製程設備簡介...............................................................42
3–2–1 低壓化學氣相沉積設備(Low Pressure-Chemical Vapor Deposition, LP-CVD)......42
3–2–2 電子束微影設備(Electron Beam Lithography, E-beam Lithography).............44
3–2–3 雙腔體乾蝕刻設備(Twin Chamber Dry Etcher).................................46
3–2–4 原子層沉積設備(Atomic Layer Deposition, ALD)..............................49
3–2–5 電子束蒸鍍系統(Electron Beam Evaporation System)..........................51
3–2–6 離子佈植機(Ion Implanter).................................................52
3–2–7 快速退火爐(Rapid annealing furnace).......................................53
3–2–8 穿透式電子顯微鏡(Transmission Electron Microscopy, TEM)....................54
3–2–9 X 射線繞射分析(X–ray scattering techniques, XRD)...........................56
3–2–10 掃描式電子顯微鏡(Scanning Electron Microscopy, SEM).......................60
3–2–11 分析型晶圓探針平台(Analytical Wafer Probe Station)........................61
3–2–12 半導體元件電性分析儀(Semiconductor Device Electrical Properties Analyzer).63
3–3 實驗步驟....................................................................65

第四章實驗結果與討論............................................................67
4–1 沉積矽/矽鍺多層結構之薄膜特性分析.............................................67
4–2 沉積堆疊式矽鍺奈米片之微觀結構分析............................................68
4–3 沉積氮化鈦薄膜用於製作閘極介電層之物性分析.....................................70
4–4 堆疊矽鍺奈米片環繞式場效電晶體之分析結果.......................................74

第五章結論.....................................................................75
參考文獻........................................................................76

參考文獻

[1] Chu, C. L. et al. “Stacked Ge-nanosheet GAAFETs fabricated by Ge/Si multilayer epitaxy”. IEEE Electron Device Lett. 39, 1133–1136. 2018. https:// doi. org/ 10. 1109/ LED. 2018. 28503 66
[2] Bera, L. K. et al. “Three dimensionally stacked SiGe nanowire array and gateall-around p-MOSFETs”. In IEDM 1–4 (San Francisco, 2006). https:// doi. org/ 10. 1109/ IEDM. (2006). 346841.
[3] Mochizuki, S. et al. “Stacked gate-all-around nanosheet pFET with highly compressive strained Si1-xGexchannel”. In IEDM 2.3.1–2.3.4 (San Francisco, 2020). https:// doi. org/ 10. 1109/ IEDM13553. 2020. 93720 41.
[4] K. Prabhakaran, F. Maeda, Y.Watanabe, and T. Ogino, Appl. Phys. Lett., 76, (2000), 2244.
[5] G. Gupta, “Carrier Transport in Dirac-Band Materials and their Device Physics”, 10.13140/RG.2.2.14293, (2015), 63206.
[6] S. Takagi, M. Noguchi, M. Kim, S. H. Kim, C. Y. Chang, M. Yokoy a, et al., “III-V/Ge MOS device technologies for low power integrated
systems”, Solid-State Electronics, vol. 125, (2016), 82.
[7] V. Pham P. “Atmospheric Pressure Chemical Vapor Deposition of Graphene. Chemical Vapor Deposition for Nanotechnology”. IntechOpen.2019. https:// doi.org/10.5772/intechopen.81293.
[8] 梁沐旺、林士欽、江源遠，“低壓化學氣相沉積應用技術”，機械工業雜誌363 期102 年6 月號，工業技術研究院機械所，2013。
[9] 陳松裕、林郁斌，“矽晶太陽電池之多晶矽鈍化層技術發展現況與趨勢分析”，經濟部能源署太陽光電技術平台建置及新材料應用開發計畫(3/3)，工研院綠能所太陽光電技術組，2021。
[10] 張評款，“以射頻磁控濺鍍法沉積鋯鈦酸鋇薄膜於ITO 基板之研究”，國立中山大學電機工程學系研究所碩士論文，2006。
[11] L.Eckertova, T. Ruzicka, “Diagnostics and Applications of Thin Films”, Ch.1&2, Institute of Physics Publishing, 1993.
[12] 彭麟皓，“矽/矽鋯多層結構高溫氧化處理之材料與機械特性分析”，國立勤益科技大學機械工程學系研究所碩士論文，2011。
[13] R. People, “Indrect Band gap of coherently strained GexSi1-x bulk alloys on <001> silicon substrates”, Physical Review B, 32, (1985), 1405.
[14] C. G. Van de Walle and R. M. Martin, “Theoretical Calculations of heterojunction discontinuities in the Si/Ge system”, Physical Review B, 34 (1986), 5621.
[15] R. People and J. C. Bean, “Band alignments of coherently strained GexSi1-x/Si heterostructures on <001> GeySi1-y substrates”, Applied Physics Letters, 48, (1986), 538.
[16] A. Levitas, “Electrical properties of germanium-silicon alloys”, Physical Review, 99, (1955), 1810.
[17] M. Glicksman, “Mobility of electrons in germanium-silicon alloys”, Physical Review, 111, (1958), 125.
[18] J.A. Moriarty, S. Krishnamurthy, “Theory of silicon superlattices：Electronic structure and enhanced mobility”, Journal of Applied Physics, 54 (1983), 1892.
[19] G.C. Osboum, “Strained-layer superlattices : A brief review”, IEEE journal of quantum electronics, 22, (1986), 1677.
[20] D.L. Harame, et al., “Si/SiGe epitaxial-base transistor-part I : materials, phys and circuits”, IEEE transactions on electron devices, 42, (1995), 455.
[21] 陸新起，“矽鍺(SiGe)技術與應用”，2003.
[22] S.M. Gates, et al., “Decomposition of silane on Si(111)-(7×7) and Si(100)-(2×1) surfaces below 500°C”, The Journal chemical physics, 92, (1990), 3144.
[23] B. Cunningham, et al., “Heteroepitaxial growth of on (100) Si by ultrahigh vacuum, chemical vapor deposition”, Applied Physics Letters, 59, (1991),
3574.
[24] Z. Ma, et al., “A high-power and high-gain X-band Si/SiGe/Si heterojunction bipolar transistor”, IBEE transactions on microwave theory
and techniques, 50, (2002), 1101.
[25] K. Rim, et al., “Fabrication and mobility characteristics of ultra thin strained-Si directly on insulator (SSDOI) MOSFETs”, in IEDM Tech. Dig., San Francisco, CA, (2003), 3.1.1.
[26] C.W. Leitz, et al., “Hole mobility enhancements and alloy scattering-limited mobility in tensile strained Si/SiGe surface channel metal oxidesemiconductor field-effect transistors”, Journal of Applied Physics, 92, (1993), 3745.
[27] S. Y. Tan, microelec. j., 38 (2007), 783.
[28] B. Y. Chen, J. L. Chen, C. L. Chu, G. L. Luo, S. Lee and E. Y. Chang, “Ge/IIIV Fin Field-Effect Transistor Common Gate Process and Numerical Simulations," Journal of Micro/Nanolithography”, MEMS, and MOEMS, 16(2), (2017), 024501.
[29] J. Robertson, P.W. Peacock, M. Houssa (Ed.), “High-κ Gate Dielectrics”, IOP, London (2003), 372.
[30] G. D. Wilk, R. M. Wallace and J. M. Anthony, J. Appl. Phys., 89, (2001), 5243.
[31] S. Swaminathan, M. Shandalov, Y. Oshima, and P. C. Mclntyre, Appl. Phys. Lett., 96 (2010), 082904.
[32] C. Rossel, A. Dimoulas, A. Tapponnier, D. Caimi, D. J. Webb, C. Andersson, M. Sousa, C. Marchiori, H. Siegwart, and R. Germann, Proceedings of the 38th European Solid-State Device Research Conference “ESSDERC 2008”, Edinburgh, UK, 15–19 September 2008 (IEEE, New York, 2008), 79-82.
[33] D. G. Schlom and J. H Haeni, MRS Bulletin, 27, (2002), 198.
[34] G. Mavrou, S. F. Galata, A. Sotiropoulos, P. Tsipas, Y. Panayiotatos , A. Dimoulas, E. K. Evangelou, J.W. Seo, and C. h. Dieker, Microelectron Eng., 84, (2007), 2324.
[35] I. H. Ohmi, S. Akama, S. Ohshima, C. Kikuchi, A. Kashiwagi, I. Taguchi, J. Yamamoto, H. Tonotani, J. Kim, Y. Ueda, I. Kuriyama, A. Yoshihara, Electron Devices Meeting, International, 8-11, (2002), 625.
[36] J. R. Hauser, Tech. Dig. Int. Electron Device Meeting, IEEE, Piscataway, NJ, (1999).
[37] A. P. Kerasidou, M. A. Botzakaki, N. Xanthopoulos, S. Kennou, S. Ladas, S. N. Georga, and C. A. Krontiras, J. Vac. Sci. Technil. A, 31, (2013), 01A126.
[38] J. Kwo, M. Hong, A. R. Kortan, K. T. Queeney, Y. J. Chabal, J. P. Mannaerts, T. Boone, J. J. Krajewski, A. M. Sergent, and J. M. Rosamilia,
“High ε gate dielectrics Gd2O3 and Y2O3 for silicon”, Appl. Phys. Lett., vol. 77, No. 1, 3 July 2000.
[39] B. W. Busch, J. Kwo, M. Hong, J. P. Mannaerts, and B. J. Sapjeta, “Interface reactions of high-k Y2O3 gate oxides with Si”, Appl. Phys.
Lett., 79, No. 15, 8 October 2001.
[40] J. Kwo. M. Hong, A. R. Kortan, K. L. Queeney, Y. J. Chabal, R. L. Opila, Jr., D. A. Muller, S. N. G. Chu, B. J. Sapjeta, T. S. Lay, J. P. Mannaerts, T. Boone, H. W. Krautter, J. J. Krajewski, A. M. Sergnt, and J. M. Rosamilia, “Properties of high k gate dielectrics Gd2O3 and Y2O3 for Si”, J. Appl. Phys., 89, No. 7, 1 April 2001.
[41] T. S. Lay, Y. Y. Liao, W. D. Liu, Y. H. Lai, W. H. Hung, J. Kwo, M. Hong, and J. P. Mannaerts, “Electrical and interfacial studies on high-k Y2O3/Si structure”, Proceedings of 2002 IEDMS, 106.
[42] C. Liao, X. Zou, C. W. Huang, J. Wang, K. Zhang, Y. Kong, T. Chen,W. W. Wu, X. Xiao, C. Jiang, and L. Liao, IEEE Electron Device Lett. 36, (2015), 1284.
[43] Y. C. Lin, H. D. Trinh, T. W. Chuang, H. Iwai, K. Kakushima, P. Ahmet, C. H. Lin, C. H. Diaz, H. C. Chang, S. M. Jang, and E. Y. Chang, IEEE Electron Device Lett. 34, (2013), 1229.
[44] W. H. Wu, Y. C. Lin, T. W. Chuang, Y. C. Chen, T. C. Hou, J. N. Yao, P. C. Chang, H. Iwai, K. Kakushima, and E. Y. Chang, Appl. Phys. Express 7 (2014), 031201
[45] P. Tsipas, S. N. Volkos, A. Sotiropoulos, S. F. Galata, G. Mavrou, D. Tsoutsou, Y. Panayiotatos, A. Dimoulas, C. Marchiori, and J. Fompeyrine, Appl. Phys. Lett, 93, (2008), 082904.
[46] Olufunsho Oladipo Olotu, Rigardt Alfred Maarten Coetzee, Peter Apata Olubambi, Tien-Chien Jen, “Operating pressure influences over micro trenches in exposure time introduced atomic layer deposition”, International Journal of Heat and Mass Transfer, vol. 153, (2020),119602.
[47] 柯志忠、林秀芬、蕭健男，“原子層沉積系統設計概念與應用”，科儀新知第二十九卷第一期，台灣儀器科技研究中心，2007。
[48] R. G. Gordon, D. Hausmann, E. Kim, and J. Shepard, Chem. Vap. Deposition, 9, (2003), 73.
[49] Debra Vogler and Paula Doe, Sol. State Technol., 46, (2003), 35.
[50] D. A. Neamen, “Semiconductor Physics and Device”, Second Edition, McGraw-Hill, New York, (2003), 469~471.
[51] Operational Manual, Epsilon 2000 Single Wifer Epitaxial Reac-tor, ASM.
[52] Capogreco, E. et al. “High performance strained germanium gate all around p-channel devices with excellent electrostatic control for sub-Jtlnm LG”. In Dig. Tech. Pap. - Symp. VLSI Technol. T94–T95 (Kyoto, Japan, 2019).https:// doi. org/ 10. 23919/ VLSIT. 2019.
[53] J. L. Chen, Y.K. Fuh, and C.L. Chu, “Effects of Etching Variations on Ge/Si Channel Formation and Device Performance”, Nanoscale Res Lett 13, (2018), 226. https://doi.org/10.1186/s11671-018-2631-1

指導教授

李雄(Shyong Lee)

審核日期

2024-6-7

推文