一個以取樣方式提供可程式化邏輯陣列功能除錯所需之完全觀察度的方法

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呂東榮(Dong-Jung Lu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

一個以取樣方式提供可程式化邏輯陣列功能除錯所需之完全觀察度的方法
(A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA)

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摘要(中)

直到現在，邏輯模擬器依然是最受歡迎的驗證工具。雖然它們可以在驗證過程中提供使用者對於被驗證之電路有完全的控制性與觀察性，但是當有大量的輸入測試訊號時，整個模擬速度將會太慢。此時若使用像可程式化邏輯陣列這樣的仿真工具，將可得到更高的模擬速度。然而在速度獲得提升之後，另外一個問題也同時產生，那就是可程式化邏輯陣列所能提供之觀察度實在太低，如此將導致驗證上的困難變高。
所以，在這篇論文中，我們提出另外一種方法來改善上述的一些短處。運用此方法，我們會記錄可程式化邏輯陣列內部的行為，之後在邏輯模擬器上跑出我們所想要之區段的波形。因為大部份的過程花費都是在可程式化邏輯陣列上，所以使用者仍可得到高速的好處。而且，對電路之完全觀察度以及相對於硬體之較佳驗證環境則可以在軟體的邏輯模擬器上獲得。
透過實驗數據的說明，可以看到使用我們所提之方法的效率。

摘要(英)

Until now, logic simulators are still the most popular verification tools. Although they can provide full controllability and observability during the verification process, its running speed is too slow for large amounts of input patterns. Using hardware emulation such as FPGA (field programmable gate array) can have higher simulation speed. However, it is very hard to debug using this approach due to poor visibility in FPGAs. Therefore, in this thesis, we propose another approach to “record” the internal behaviors of an FPGA and “replay” the interesting period of time in a software simulator. In this way, we can still have high simulation speed because most simulation efforts are still finished in the FPGA. Moreover, full visibility and better debugging environment can be provided in the software simulation. The experimental results have shown the efficiency of using our approach.

關鍵字(中)

★ 取樣
★ 可程式化邏輯陣列
★ 重建

關鍵字(英)

★ snapshot
★ FPGA
★ reconstruct

論文目次

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 6
Chapter 2 Related Works 7
2.1 Introduction 7
2.2 “Readback” in Advanced FPGAs 7
2.3 Signal Tap Ⅱ from Altera 8
2.4 Chip Scope Pro with Trace Port Analyzer 11
2.5 IP Cores Provided by Temento 14
2.6 Scan-Chain Based Watch-Points Technique 16
2.7 Simulation and Reconstruction on Simulator 18
2.8 Xcite Simulation Acceleration Platform 21
Chapter 3 Snapshot and Reconstruction Mechanisms 23
3.1 Introduction 23
3.2 System Diagram of Reconstruction 26
3.3 The Size of Trace Buffers 27
3.4 Tradeoff between Some Major Parameters 29
3.5 Summary 31
Chapter 4 The Implementation of Our Research 32
4.1 Introduction 32
4.2 The Major Tools for Development 32
4.3 The Nios Development Board_ APEX Edition 33
4.4 The Architecture of Our Implementation 37
4.5 Summary 43
Chapter 5 Experimental Results 44
5.1 Introduction 44
5.2 Comparison of Speed and Efficiency 44
5.3 Comparison of Hardware Overhead 46
Chapter 6 Conclusions 49
Reference ………………………………………..50

參考文獻

[1] Cadence Design System Corporation., Palladium Data sheet, http://www.cadence.com/datasheets/4510C_IncisivePalladium_fnl.pdf
[2] Mentor Graphics Corporation, Vstation Pro Emulator, http://www.mentor.com/vstation/vstation_pro.html
[3] IEEE, Standard 1149.1a, IEEE standard Test Access Port and Boundary-Scan Architecture, revised, 1993.
[4] Altera Corporation, Signal Tap II Embedded Logic Analyzer, http://www.altera.com/products/software/pld/design/verification/signaltap2
/sig-index.html
[5] Xilinx Corporation, Chip Scope On Chip Debug Integrated Logic Analyzer, http://www.xilinx.com/ise/verification/chipscope_pro_glance2.htm
[6] Anurag Tiwari, Karen A. Tomko, “Scan-chain Based Watch-points for Efficient Run-Time Debugging and Verification of FPGA Designs”, ASPDAC, 2003.
[7] Joshua Marantz, “Enhanced Visibility and Performance in Functional Verification by Reconstruction”, Proc. DAC’98, San Francisco, CA
[8] ITC’99 test suite, Electric CAD & Reliability Group, http://www.cad.polito.it/tools/#bench
[9] Temento Corporation, DiaLite Instrumentation for Verification on FPGAs, http://www.temento.com/solutions/fpga.php
[10] Michael L. Bushnell and Vishwani D. Agrawal, “Essentials of Electronic Testing”, Kluwer Academic Publishers, 2000.
[11] Xilinx Corporation, Readback Function, XAPP138 : Virtex Configuration and Readback, http://www.xilinx.com/ipcenter/catalog/search/reference
/xapp138_virtex_configuration_and_readback.htm
[12] Agilent Technologies, Trace Port Analyzer for On Chip Design Verification With Xilinx FPGAs, http://cp.literature.agilent.com/litweb/pdf/5988-9434EN.pdf
[13] Altera Corporation, Quartus ⅡDesign Software for Altera FPGAs, http://www.altera.com/literature/manual/intro_to_quartus2.pdf
[14] Model Technology Corporation, ModelSim 5.5 e, Simulation Software, http://www.model.com/products/se.asp
[15] Altera Corporation, Nios Development Board_APEX Edition, http://www.altera.com/literature/ds/ds_nios_board_apex_20k200e.pdf
[16] Altera Corporation, ByteBlasterMV Parallel Port Download Cable, http://www.altera.com/literature/ds/dsbytemv.pdf
[17] Integrated Device Technology, Data Sheet of 3.3 V CMOS Asynchronous SRAM, http://www1.idt.com/pcms/tempDocs/71V016_DS_6428.pdf
[18] Flottes, M. L., Pires, R., Rouzeyre, B., Volpe, L., “Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique”, Design, Automation and Test in Europe, 1998.
[19] Mukherjee, D., Pedram, M., Breuer, M., “Control Strategies for Chip-based DFT/BIST Hardware”, Test Conference, 1994.
[20] Chih-Chang Lin, Marek-Sadowska, M., Lee, M. T.-C., Kuang-Chien Chen, “Cost-free Scan: A Low Overhead Scan Path Design”, Computer-Aided Design of Integrated Circuits and Systems”, 1998.
[21] Verisity Corporation, Xcite Simulation Acceleration platform, http://www.verisity.com/products/xcite.html

指導教授

劉建男(Chien-Nan Liu)

審核日期

2004-7-7

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