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姓名	陳昭安(Chao-An Chen)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統 (A 30phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery)
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摘要(中)	隨著製成技術的進步以及各個運算處理速度的提升，傳送接收系統應用在高速上是未來的趨勢，例如應用在乙太網路及光纖網路上的如10GBase-LX4、OC192、OC768等。而著重在有線或是匯流排上的應用則有USB2.0、IEEE1394、SERIAL-ATA等系統，在此系統當中所傳送的資料速度多為Gb/s的等級。在高速傳送上，會有更多的困難需要克服。例如雜訊的處理，時脈產生器產生高速時脈等等的問題。本論文試著採用三倍超取樣的技術應用在接收端的電路上，並試著符合到PCI-Express II的規格。 本論文是將接收端的電路應用在5Gb/s的資料傳送系統上，達到一個高速5Gb/s串列資料，經由接收端電路，解回十組並列500Mb/s的資料。其中，鎖相迴路(PLL)作為系統上的時脈產生器，用來對於輸入的資料做取樣的動作。而系統當中所需要切割出微小的時脈延遲來調整鎖相迴路的參考時脈相位則採用Blender 的電壓切割方式，切割出15ps左右的延遲相位，以達到系統上所規定的頻寬。三倍超取樣的方式比起兩倍超取樣來說可以達到較小的靜態相位誤差，且比起四倍或五倍的方式複雜度不至於太大。 在整體電路實現上，我們採用0.13-um製程，1.2-V的電源供應來實現我們接收端的電路。
摘要(英)	With the progress in the CMOS process technologies and the operating speed of the processor, high speed links in the transmitter and receiver system is the trend of the future. For example, 10Gbase-LX4, OC192, OC768 are used in Gigabit Ethernet and Fiber Channel; USB2.0, IEEE1394 and SERIAL-ATA are used in wire or bus serial links. Most of the system operate at the data rate attain to the level of Gb/s. With the increased operation frequency, the difficulties in the system design are also increased. These difficulties include noise handling and the generation of the sampling clock at high frequency in receiver side, etc. The thesis adopts 3X over-sampling techniques in the receiver circuit and tries to meet the specification of PCI- Express II. The thesis design a receiver circuit which is used in the one serial in data with 5Gb/s and retime them to 10 500Mb/s parallel out data. PLL circuit is used as the clock generation and the output clock signals of PLL are used to sample the input data. The small phase delay circuit is implemented by Blender delay to make approximately 15ps delay and is used to tuning the phase of PLL’s reference clock. The need of small phase delay is because of the specification of CDR bandwidth. Adopting the 3X over-sampling is considered that 2X over-sampling system has larger static phase error and circuit in 4X or 5X is too complex. The receiver system in the thesis is implemented with a 0.13-um CMOS technology with a 1.2V supply power.
關鍵字(中)	★ 時脈回復系統 ★ 三倍超取樣 ★ 鎖相迴路	關鍵字(英)	★ clock data recovery ★ PLL ★ Over-Sampling
論文目次	Abstract ii Table of Contents iii List of Tables vi List of Figures vii Chapter 1 1.1 Motivation 1 1.2 Thesis organization 1 Chapter 2 2.1 Link Basic 3 2.2 Serial Links V.S. Parallel Links 4 2.3 Noise Source in Channel Link 6 2.3.1 Channel Attenuation and Inter-Symbol Interference 6 2.3.2 Reflection 6 2.3.3 Power Supply Noise 7 2.4 Architecture of Clock and Data Recovery 7 2.4.1 PLL Based CDR 8 2.4.2 Bland Over-Sampling CDR 13 Chapter 3 3.1 Comparison between Traditional and Proposed CDR 15 3.2 Specification of CDR in PCI-Express II 16 3.3 PLL Design in Over-Sampling CDR 18 3.3.1 Phase Frequency Detector Circuit 19 3.3.2 Charge Pump Circuit 19 3.3.3 Loop Filter 20 3.3.4 Voltage Control Oscillator 20 3.3.5 Divider 21 3.3.6 Linear Analysis of PLL Circuit 21 3.4 Proposed Over-Sampling CDR 25 3.4.1 Operation of 3X Over-Sampling CDR 25 3.4.2 Jitter Tolerance Bandwidth Analysis 28 3.4.3 Timing Diagram in 3X Over-Sampling CDR 32 Chapter 4 4.1 PLL Circuit 34 4.1.1 Phase Frequency Detector 34 4.1.2 Charge Pump Circuit 36 4.1.3 Voltage Control Oscillator 38 4.1.4 Divider Circuit 40 4.1.5 Lock Detector 41 4.1.6 PLL Circuit Simulation 43 4.2 CDR Digital Circuit 45 4.2.1 Sampler Circuit 45 4.2.2 Control Logic 46 4.2.3 Blender Delay Element 48 4.2.4 Phase Shifter 52 4.2.5 Phase Selector 54 4.2.6 Input and Output Buffer 54 4.3 Simulation Result of CDR 55 4.4 Layout of CDR 59 Chapter 5 5.1 Experimental Results of the Input 2.5Gb/s Serial Data and Four 625Mb/s Parallel Out CDR 61 5.1.1 Measurement Result of PLL 62 5.1.2 Measurement Result of CDR 63 5.2 Experimental Results of the Input 5Gb/s Serial Data and Ten 500Mb/s Parallel Out CDR 64 5.2.1 Measurement Result of PLL 64 5.2.2 Measurement Result of CDR 66 Chapter 6 6.1 Conclusions 70 6.2 Recommendations for Future Works 70 References 72 Appendix A 75
參考文獻	[1] R. Mooney, et al.,”A 900Mb/s bidirectional signaling scheme,” IEEE Jorunal of Solid-State Circuits, vol.30, no.12, pp.1538-1543, Dec. 1995 [2] M. Galles, et al.,”Spider: a high-speed network interconnect,” IEEE Micro, vol.17, no. 1,pp.34-39, Jan-Feb. 1997 [3] Media Access Contro(MAC) Parameters, Physical Layer, and Management Parameter for 10Gb/s Operation, IEEE Draft p802.3ae/D3.3, 2000. [4] K.Yukimatsu and Y. Shimazu, “Optical interconnections in switching system”, IEICE Trans. Electron., vol. E77-C, no. 1, pp.2-8, Jan.1994. [5] Jaeha Kim, “Design of CMOS Adaptive-Supply Serial Links”, a dissertation submitted to the Department of Electrical Engineering and the Committee on Graduate Studies of Stanford University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy, Dec. 2002 [6] John G. Maneatis, “Low-jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE Jorunal of Solid-State Circuits, vol.31, no. 11, pp.1723-1732, Nov. 1996 [7] Tai-Cheng Lee and Behzad Razavi, Fellow, IEEE, “A Stabilization Technique for Phase-Locked Frequency Synthesizers,” IEEE Jorunal of Solid-State Circuits, vol.38, no. 6, pp. 888-894, June. 2003 [8] Mozhgan Mansuri, et al.,”A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply-Noise Compensation”, IEEE Jorunal of Solid-State Circuits, vol. 38, no. 11, pp.1804-1812, Nov. 2003 [9] Seema Butala Anand and Behzad Razavi, “A CMOS Clock Recovery Circuit for 2.5-Gb/s NRZ Data,” IEEE Jorunal of Solid-State Circuits, vol.36, no. 3, pp. 432-439, March. 2001 [10] Sang-Hyun Lee, et al.,”A 5Gb/s 0.25-um CMOS Jitter-Tolerant Variable-Interval Oversampling Clock/Data Recovery Circuit,” IEEE Jorunal of Solid-State Circuits, vol. 37, no. 12, pp. 1822-1830, Dec. 2002 [11] Behzad Razavi, “Challenges in the Design of High-Speed Clock and Data Recovery Circuits” IEEE Communications magazine, Aug. 2002 [12] Evelina Fai-Yee Yeung, “Design of High-Performance and Low-Cost Parallel Links”, a dissertation submitted to the Department of Electrical Engineering and the Committee on Graduate Studies of Stanford University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy, Jan. 2002 [13] Koon-Lun Jackie Wong, et al.,”A 27-mW 3.6-Gb/s I/O Transceiver” IEEE Jorunal of Solid-State Circuits, vol. 39, no. 4, pp. 602-612, April. 2004 [14] Sun-Ping Chen,”Design and implementation of 3.125-GB/s Clock Data Recovery Circuit”,a thesis submitted to the Graduate Institute of Electronic Engineering , National Taiwan University in Fulfillment of the Requirements for the Degree of Master of Science in Electrical Engineering, June. 2003 [15] Jung-Wei Chen,”A Tracking Data Recovery System for Inter-Chip Signaling”, a thesis submitted to the Graduate Institute of Electronic Engineering , National Taiwan University in Fulfillment of the Requirements for the Degree of Master of Science in Electrical Engineering, June. 2000 [16] J. Savoj and B. Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half Rate Linear Phase Detector,” IEEE Jorunal of Solid-State Circuits, vol. 36, no. 5, pp. 761-767, May. 2001 [17] Jaeha Kim and Deog-Kyoon Jeong, “Multi-Gigabit-Rate Clock and Data Recovery Based on Blind Oversapmling,”IEEE Communications Magazine, Dec. 2003 [18] Yoshiharu kudoh, et al.,”A 0.13-um CMOS 5-Gb/s 10-m 28AWG Cable Transceiver With No-Feedback-Loop Continuous-Time Post-Equalizer,” IEEE Jorunal of Solid-State Circuits, vol. 38, no. 5, pp. 741-746, May. 2003 [19] Jong-Sang Choi, et al.,”A 0.18-um CMOS 3.5-Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Control Method,” IEEE Jorunal of Solid-State Circuits, vol. 39, no. 3, pp. 419-425, March. 2004 [20] Jinwook Kim, et al.,”A Four-Channel 3.125-Gb/s/ch CMOS Serial-Link Transceiver With a Mixed-Mode Adaptive Equalizer,” IEEE Jorunal of Solid-State Circuits, vol. 40, no. 2, pp. 462-471, Feb. 2005 [21] B. Razavi, “Design of Integrated Circuits for Optical Communication,” McGraw-Hill, 2003 [22] Youngdon Choi, et al.,”Jitter Transfer Analysis of Tracked Oversampling Techniques for Multigigabit Clock and Data Recovery,” Invited paper, IEEE Transactions on Circuit and Systems, vol. 50, no. 11, pp. 775-783, Nov. 2003 [23] Yoshio Miki, et al.,”A 50-mW/ch 2.5-Gb/s/ch Data Recovery Circuit for the SFI-5 Interface With Digital Eye-Tracking,” IEEE Jorunal of Solid-State Circuits, vol. 39, no. 4, pp. 613-621, April. 2004 [24] Declan Dalton, et al.,”A 12.5-Mb/s to 2.7-Gb/s Continuous-Rate CDR With Automatic Frequency Acquisition and Data-Rate Readback,” IEEE Jorunal of Solid-State Circuits, vol. 40, no. 12, pp. 2713-2725, Dec. 2005 [25] Yongsam Moon, et al.,”A 0.6-2.5-GBaud CMOS Tracked 3x Oversampling Transceiver With Dead-Zone Phase Detection for Robust Clock/Data Recovery,” IEEE Jorunal of Solid-State Circuits, vol. 36, no. 12, pp. 1974-1983, Dec. 2001 [26] Hideyuki Nosaka, et al.,”A 10-Gb/s Data-Pattern Independent Clock and Data Recovery Circuit With a Two-Mode Phase Comparator,” IEEE Jorunal of Solid-State Circuits, vol. 40, no. 2, pp. 192-197, Feb. 2005 [27] Abdulkerim L. Coban, et al.,”A 2.5-3.125-Gb/s Quad Transceiver With Second-Order Analog DLL-Based CDRs,” IEEE Jorunal of Solid-State Circuits, vol. 40, no. 9, pp. 1940-1947, Sep. 2005 [28] “An Analysis and Performance Evaluation of a Passive Filter Design Techniques for Charge Pump PLL’s,” National Semiconductor application note, July 2001. [29] Bruno W. Garlepp, et al.”A portable Digital DLL for High-Speed CMOS Interface Circuits,” IEEE Jorunal of Solid-State Circuits, vol. 34, no. 5, pp. 632-644, May. 1999 [30] Yu-Tang Hsieh,”CMOS Precise Delay Generator and Its Application in Timing Recovery”,a thesis submitted to the Graduate Institute of Electronic Engineering , National Chiao Tung University in Fulfillment of the Requirements for the Degree of Master of Science in Electrical Engineering, June. 2001
指導教授	鄭國興(Kuo-Hsing Cheng)	審核日期	2006-7-17
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