3-10 GHz 寬頻低雜訊放大器 ;3-10 GHz Wideband Low Noise Amplifiers

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Title:	3-10 GHz 寬頻低雜訊放大器;3-10 GHz Wideband Low Noise Amplifiers
Authors:	蔡承修;Cheng-Hsiu Tsai
Contributors:	電機工程研究所
Keywords:	低雜訊放大器;超寬頻系統;ultra-wideband;low-noise amplifier
Date:	2008-06-30
Issue Date:	2009-09-22 12:12:13 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	本論文是以TSMC 0.18 um CMOS 製程，研製應用於超寬頻(UWB)系統之寬頻低雜訊放大器，電路的設計主要考量為低成本和低功率，朝向商品化邁進。論文中使用兩種電路架構，一為採用電感電容濾波器形式做寬頻輸入匹配，一為使用共閘極架構做為輸入端。第一部份實現兩個寬頻低雜訊放大器，皆採用電感電容濾波器形式做寬頻輸入匹配，在其中一個電路上搭配達靈頓對架構來增加截止頻率提高增益。未搭配達靈頓對架構的寬頻低雜訊放大器，在直流功率消耗15.4 mW時可以得到最大增益為11 dB，3-dB頻寬為3.9 – 10.3 GHz，最低雜訊指數為4.5 dB，在頻帶內輸入反射損耗均小於-13 dB，三階截斷點大於-9 dBm，其晶片面積為0.86 mm2。而搭配達靈頓對架構的寬頻低雜訊放大器，在直流功率消耗20.3 mW時可以得到最大增益為13 dB，3-dB頻寬為3.0 – 10.7 GHz，最低雜訊指數為3.57 dB，在頻帶內輸入反射損耗均小於-8 dB，三階截斷點大於-14 dBm，其晶片面積為0.78 mm2。第二個部份的寬頻低雜訊放大器，為了減少晶片面積和降低功率消耗，使用共閘極架構具備寬頻匹配特性做為輸入端，並利用電流重複利用的技術提昇增益且節省直流功率的消耗。在直流功率消耗7.2 mW 時可以得到最大增益為14.3 dB，3-dB頻寬為2.7 – 8.4 GHz，最低雜訊指數為3.98 dB，在頻帶內輸入反射損耗均小於-8 dB，三階截斷點大於-12.5 dBm，其晶片面積為0.78 mm2。 In this thesis, we design three broadband low noise amplifiers (LNAs) for ultra-wideband (UWB) communication systems, which are implemented in TSMC 0.18 um CMOS technology. The design of the amplifiers concentrates on low power-consumption and low costs as well. In the first section, two amplifiers are designed on the basis of LC high-pass filters which are used for wideband impedance match. The two amplifires are designed with and without Darlington pair, respectively. In the second circuit, a Darlington pair is used at the second stage to achieve high gain performance. The measurement of the first LNA without Darlington pair shows that the maximum gain is 11 dB, 3-dB bandwidth is from 3.9 GHz to 10.3 GHz, the minimum noise figure is 4.5 dB, S11 is less than -13.4 dB, IIP3 is better than -9 dBm, and the total power consumption is 15.4 mW. The chip size is 0.86 mm2. For the second LNA with Darlington pair, the measurement shows that the maximum gain is 13 dB, 3-dB bandwidth is from 3.0 GHz to 10.7 GHz, the minimum noise figure is 3.57 dB, S11 is less than -8 dB, IIP3 is better than -14 dBm, and the total power consumption is 20.3 mW. The chip size is 0.78 mm2. In the second section, a low-power consumption and high-gain broadband LNA utilizing a common-gate stage connected with a common-source stage by using a current-reused structure is proposed. The measured maximum gain is 14.2 dB, 3-dB bandwidth is from 2.7 GHz to 8.4 GHz, the minimum noise figure is 3.93 dB, S11 is less than -8 dB, IIP3 is better than -12.5 dBm, and the total power consumption is 7.2 mW. The chip size is 0.78 mm2.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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