近三十年來，半導體業不斷地追求更高的元件密度與更快的操作速度，為了 達到這兩個目的，金氧半場效電晶體( Metal Oxide Semiconductor Field Effect Transistor，MOSFET )的通道長度不斷地向下微縮。在西元2008 年，Intel 已經 成功的發展出通道長度僅有35 nm 的MOSFET。儘管Intel 成功地不斷將通道向 下微縮，但微縮的過程是愈來愈艱辛。物理學家更大膽的預期MOSFET 通道微 縮的終點將止於約10 nm，因為這個尺度下的通道長度只有幾個原子直徑，造成 場效電晶體的微縮面臨瓶頸。為了繼續將元件尺寸向下微縮，達到更小面積、更 高操作速度的半導體元件，近年來量子元件的研究如雨後春筍般的出現。 在此篇論文中，著重於改善本實驗室上一代自我對準電極SET/SHT 在奈米 線( nanowire )蝕刻時良率不高、穿隧接面厚度過厚與源極與汲極摻雜濃度不足等 缺點。本論文成功的克服奈米尺度下蝕刻SOI wafer ( silicon on insulator ) 側蝕嚴 重的問題，大幅改善蝕刻時的良率，並在電性量測上觀察到由不對稱穿隧接面所 造成的兩個截然不同的ID-VG 譜線( spectrum )，且更深入探討量子點內的量子效 應。 In the recent thirty years, the semiconductor industries pursue higher density of devices and operation speed without end. In order to achieve these goals mentioned above, the reductions of channel lengths of MOSFET are shorten incessantly. In 2008, Intel has announced they developed the 35 nm gate length of MOSFET successfully. Although they succeeded in decreasing the critical dimension, the develop procedure has been much more difficult than before. The end of the channel length shortening is expected to be 10 nm by physicists. Because the dimension of channel length is only several times of an atomic diameter, the reason causes the bottleneck appearing in the road of critical dimension shortening. In order to short the device dimension, speed up operation speed, and decrease device area, the research of quantum devices are published very often. This thesis focuses on rising the low yield in nanowire etching, decreasing the tunneling barrier thickness and solving the source/drain lack of dopant issue. Thisthesis has conquered the tremendous lateral etching issue under etching SOI wafer in nanoscale. The characterizations of asymmetric tunneling barrier are observed obviously under room-temperature.
