適用於平行處理及排程技術的無衝突定址法演算法之快速傅立葉轉換處理器設計; A Conflict-Free Memory Addressing Scheme For Fast Fourier Transform Processors With Parallelism And Scheduling Techniques

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题名:	適用於平行處理及排程技術的無衝突定址法演算法之快速傅立葉轉換處理器設計;A Conflict-Free Memory Addressing Scheme For Fast Fourier Transform Processors With Parallelism And Scheduling Techniques
作者:	林忠毅;Chung-yi Lin
贡献者:	電機工程研究所
关键词:	快速傅立業轉換;Fast Fourier Transform;FFT
日期:	2009-07-07
上传时间:	2009-09-22 12:15:06 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	近年來正交分頻多工系統(orthogonal frequency division multiplexing)通訊系統蓬勃發展，如digital video broadcasting-terrestrial (DVB-T)，handheld terminals (DVB-H)，3GPP long term evolution (3GPP-LTE)，ultra wide band (UWB)，802.16e/m和802.20等，快速傅立業轉換處理器是應用在正交分頻多工系統中重要的一塊電路。本篇論文提出高基數快速傅立業轉換處理器結合多路徑延遲交換器架構與記憶體基底架構，利用管線式之多路徑延遲交換器架構其操作時脈可以小於或等於系統的操作頻率，減少快速傅立業轉換處理器的運算時間以降低功率消耗，而運用記憶體基底架構使用較少的蝴蝶運算器的優點來減少蝴蝶運算器數目。除此之外，提出一種快速傅立業轉換之無衝突定址方式來達到最小的記憶體需求與連續運算，並將複數乘法運算重新排程以提高複數乘法器的使用率來降低複數乘法器的數目，設計一個能運算Radix-2、Radix-22、Radix-23的混基數多路徑延遲交換器電路，使設計的可變長度快速傅立業轉換處理器可以運算64~4096點。使用TSMC 0.18μm CMOS製程實現1024點的快速傅立業轉換處理器，在30MHz的速度下功率消耗為70.5mW，晶片中心的尺寸為1.561.56mm2。 Orthogonal frequency division multiplexing (OFDM) communication systems became popular in recent years, like digital video broadcasting-terrestrial (DVB-T), handheld terminals (DVB-H), 3GPP long term evolution (3GPP-LTE), ultra wide band (UWB), 802.16e/m and 802.20. In orthogonal frequency division multiplexing communication systems, a Fast Fourier transform (FFT) processor is an important kernel. In this thesis, we proposed a high radix FFT processor that combines multi-path delay commutator architecture with memory-based architecture. By using pipelined multi-path delay commutator FFT architecture, the operation clock frequency can be set less than or equal to the system sampling rate and thus the power consumption can be reduced. We also take advantage of the memory-based architecture to save the number of butterfly units. Besides, a novel conflict-free memory addressing scheme is proposed to accomplish this continuous-flow FFT processor with the least requirement of the memory. We also schedule the complex multiplication to reduce the required complex multipliers and increase their utilization. A mixed-radix multi-path delay commutator is designed to calculate radix-2, radix22 and radix23 algorithm so that our proposed FFT processor can provide FFT computations from 64 to 4096 points. We have implemented the proposed FFT processor of 1024 points in TSMC 0.18μm CMOS technology. The power consumption is 70.5mW at 30-MHz operating frequency and 1.8-V supply voltage with core area of 1.561.56mm2.
显示于类别:	[電機工程研究所] 博碩士論文

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