3GPP LTE正交分頻多工存取下行傳輸之接收端細胞搜尋與同步的設計與實現 ; Design and Implementation of Cell Search and Synchronization in a 3GPP Long Term Evolution Downlink OFDMA Receiver

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題名:	3GPP LTE正交分頻多工存取下行傳輸之接收端細胞搜尋與同步的設計與實現;Design and Implementation of Cell Search and Synchronization in a 3GPP Long Term Evolution Downlink OFDMA Receiver
作者:	張翔瑋;Hsiang-wei Chang
貢獻者:	電機工程研究所
關鍵詞:	正交分頻多工存取;OFDMA;synchronization;cell search;3GPP LTE
日期:	2010-03-19
上傳時間:	2010-06-11 16:20:17 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	傳收端間震盪器和時序的不協調造成載波頻率和相位的誤差，使得同步的處理在所有的訊號傳輸系統是不可或缺的功能區塊。在手機系統中，用戶端必須執行同步與細胞搜尋的程序來獲得符元邊界、訊框時序、載波頻率偏移和細胞識別碼等資訊。本篇論文主要是基於在3GPP LTE下行傳輸規格所提出的一種細胞搜尋與同步的方法。它一共分為三個步驟: 首先，我們先使用延遲相關方法找出符元邊界和小數部份的載波頻率偏移以便繼續下一個在頻域上的步驟。其次，我們提出一種利用主要同步通道之訊號相位差來同時偵測整數部份載波頻率偏移和分區細胞索引N_ID^((2))的方法，結果顯示能有效地抵抗符元時序的誤差以及高速時選衰退的通道效應。最後，我們提出一種不需要具體地求出的真正的通道響應的方法來得出訊框時序和細胞分群識別碼N_ID^((1))的方法。模擬結果所得出的低錯誤率也證明了所提出的方法跟傳統的方法比較起來較為有效率且較為穩固, 演算法的複雜度也可降低約80%左右。在硬體的實作上，採用硬體共享的概念，將偵測N_ID^((2))和N_ID^((1))的乘加器共用，來降低硬體的複雜度，得到了約50%的改善，最後完成其系統電路的設計及模擬。 The synchronization issue is inevitable in all signal transmission systems. Oscillator mismatch causes carrier and clock frequency/phase errors are main problems. In cellular systems, a user equipment must activate a cell search procedure when startup to acquire symbol timing, frame timing, carrier frequency offset and cell ID information. This thesis presents a novel synchronization and cell search procedure in 3GPP LTE downlink OFDMA systems. The proposed cell search procedure contains three steps. In the beginning, delay and correlate methods are adopted to estimate symbol timing and fractional carrier frequency offset so that frequency-domain signal processing can be performed subsequently. Secondly, a new joint detection method for integer carrier frequency offset and sector cell index information is proposed, which is shown to be capable of resisting symbol timing error in highly time-selective fading channels. Finally, we also proposed a detection method for frame timing and cell ID group information without explicit channel estimates. Simulation results demonstrate that the proposed scheme with lower detection error probability is effective and robust compared with some conventional approaches. Also, its arithmetic complexity can be reduced about 80%. The hardware sharing technique is employed while implementing this system to reduce hardware costs. For cell search procedures, we saved 50% (adders/storages). The performance of the implemented design has been verified and only tiny implementation loss is suffered.
顯示於類別:	[電機工程研究所] 博碩士論文

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