應用於PCI; Express Generation II之5-Gb/s 無電感式類比等化器的設計與實現 Design and Implementation of 5-Gb/s Inductorless Analog Equalizer for PCI Express Generation II

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Title:	應用於PCI;Express Generation II之5-Gb/s 無電感式類比等化器的設計與實現 Design and Implementation of 5-Gb/s Inductorless Analog Equalizer for PCI Express Generation II
Authors:	吳彥學;Yen-Hsueh Wu
Contributors:	電機工程研究所
Keywords:	等化器;無電感;高速串列傳輸;equalizer;inductorless;high speed serial links
Date:	2009-12-13
Issue Date:	2010-06-11 16:20:46 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	近年來由於網路和處理器快速的發展，使得快速傳輸大量資料已成為傳輸系統的主要動機，因此傳統的平行匯流排逐漸的被高速串列傳輸系統所取代。但是，當系統的操作頻率在Gigahertz 等級時，高頻的資料經過通道之後會失真及衰減。因此本論文希望實現一個5-Gb/s無電感式類比等化器來補償通道的損失，並能應用於 PCI Express Generation II的系統中。本論文提出的無電感式類比等化器可以補償PCI Express Generation II 在2.5-GHz時14-dB的通道損失。在Equalizing Filter的部分使用Low Voltage Zero Generator (LVZG)，其沒有使用電感就能在高頻產生高增益。並且使用Spectrum-balancing Technique來移除掉Regulating Comparator。在Power Detector (POD)的部份結合Current Steering Technique和Pre-amplifier來增大振幅，因此能減輕Error Amplifier所需要的增益。本晶片以 TSMC 0.18-μm 1P6M CMOS 製程來實現，在工作電壓為 1.6-V時，其功率消耗為 17.6-mW(不含Output Buffer)，當晶片包含 PAD 時，晶片總面積為 0.54-mm2，而核心部分的面積為 0.1-mm2(包含Output Buffer)，輸出峰對峰(Peak-to-peak)的抖動量為0.28-UI。 In recent years, due to rapid development of network and processor, transmit a lot of data quickly becomes the main motivation of transmission system. Therefore, conventional parallel bus is replaced gradually by high-speed serial link transmission system. But, when the system operates at gigahertz level frequency, the data of high frequency component pass through the channel will distort and degrade. For this reason, this thesis hopes to realize a 5-Gb/s inductorless analog equalizer to compensate channel loss, and can be applied in PCI Express Generation II system. This thesis proposes an inductorless analog equalizer that compensates for the PCI Express Generation II channel loss of 14-dB at 2.5-GHz. This equalizing filter uses low voltage zero generator (LVZG) to generate high-frequency gain boosting without using inductors. The spectrum-balancing technique eliminates the needing for regulating comparator. The power detector (POD) combines current steering technique and pre-amplifier circuit to enhance the voltage swing, therefore relax the gain requirement of error amplifier. The test chip is implemented in TSMC 0.18-μm 1P6M CMOS technology. It works at power supply 1.6-V with 17.6-mW (excluding the output buffer). The total chip area is 0.54-mm2 with pads, the core area is 0.1-mm2 (including output buffer), and output peak-to-peak jitter is 0.28-UI.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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