A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design

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題名:	A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design
作者:	Jou,SJ;Chen,CY;Yang,EC;Su,CC
貢獻者:	電機工程研究所
關鍵詞:	CMOS;LOGIC
日期:	1997
上傳時間:	2010-06-29 20:20:55 (UTC+8)
出版者:	中央大學
摘要:	This paper proposes a new pipelined full-adder circuit structure for the implementation of pipelined arithmetic modules. With both static and dynamic structures, it has the advantages of high operational speed, smallest transistor count, and the low power/speed ratio, The adder cell is then used to design a pipelined 8 x 8-b multiplier-accumulator (MAC). In this MAC, a special pipelined structure is designed to reduce the latency, The MAC is fabricated in a 0.8-mu m single-poly-double-metal CMOS process, The post-layout simulation shows that the pipelined 1-b full adder can work up to 350 MHz with a 3 V power supply, The whole MAC chip that contains 4200 transistors is measured to operate a 125 MHz using 3.3 V power supply.
關聯:	IEEE JOURNAL OF SOLID-STATE CIRCUITS
顯示於類別:	[電機工程研究所] 期刊論文

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